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1. SUMMARY
1.5.3 Module information
The (R)s in the table designate read only, while the (W)s designate write only capability.
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
020000
Bus type (R)
Implemented CH
information (R)
Interrupt output mask
information (R)
Reserved
Board ID information (R)
020001 Reserved
Number of SSCNET
lines (R)
020002
Reserved
020003
020004 Reserved
Signal during interrupt
output (R)
020005
Reserved
020006
020007
020008 Reserved
Interrupt signal clear
register (1CH) (W)
020009
Reserved
02000A
02000B
02000C
02000B
02000C
Reserved
02000D
Reserved
02000E
02000F
(1) Board ID information (address 020000h)
Status set with the dip switch is displayed.
bit1 bit0
Content
0 0
0
0 1
1
1 0
2
1 1
3
(2) Interrupt output mask information (address 020000h)
Status set with the dip switch is displayed.
bit3 Content
0 Invalid
1 Valid
1 Valid
(3) Implemented CH information (address 020000h)
bit5
bit4
Content
0 0
1CH
0 1
Reserved
1 0
Reserved
1 1
Reserved
(4) Bus type (address 020000h)
bit7
bit6
Content
0 0
PCI
bus
0 1
Reserved
1 0
PCI
Express
®
bus
1 1
Reserved