Техническая Спецификация для AMD 8151
24888 Rev 3.03 - July 12, 2004
AMD-8151
TM
AGP Tunnel Data Sheet
14
The first calibration cycle occurs approximately 4 milliseconds after the deassertion of RESET# (whether AGP
2.0 or 3.0 signaling is enabled).
2.0 or 3.0 signaling is enabled).
5
Registers
5.1
Register Overview
The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers
to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration
space is typically accessed by the host through IO cycles to CF8h and CFCh. There is also memory space and
indexed address space in the IC.
to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration
space is typically accessed by the host through IO cycles to CF8h and CFCh. There is also memory space and
indexed address space in the IC.
5.1.1
Configuration Space
The address space for the IC configuration registers is broken up into busses, devices, functions, and, offsets, as
defined by the link specification. It is accessed by HyperTransport™ technology-defined type 0 configuration
cycles. The device number is mapped into bits[15:11] of the configuration address. The function number is
mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:2] of the configuration
address.
defined by the link specification. It is accessed by HyperTransport™ technology-defined type 0 configuration
cycles. The device number is mapped into bits[15:11] of the configuration address. The function number is
mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:2] of the configuration
address.
The following diagram shows the devices in configuration space as viewed by software.
Device A, above, is programmed to be the link base UnitID and device B is the link base UnitID plus 1.
5.1.2
Register Naming and Description Conventions
Configuration register locations are referenced with mnemonics that take the form of Dev[A|B]:[7:0]x[FF:0],
where the first set of brackets contain the device number, the second set of brackets contain the function num-
ber, and the last set of brackets contain the offset.
where the first set of brackets contain the device number, the second set of brackets contain the function num-
ber, and the last set of brackets contain the offset.
Other register locations (e.g. memory mapped registers) are referenced with an assigned mnemonic that speci-
fies the address space and offset. These mnemonics start with two or three characters that identify the space
followed by characters that identify the offset within the space.
fies the address space and offset. These mnemonics start with two or three characters that identify the space
followed by characters that identify the offset within the space.
Register fields within register locations are also identified with a name or bit group in brackets following the
register location mnemonic.
register location mnemonic.
Figure 2: Configuration space.
Primary bus
AGP Device
DevA:0xXX
Device header
First device
Function 0
Secondary bus
AGP Slot
AGP Bridge
DevB:0xXX
Bridge header
Second device
Second device
Function 0