Техническая Спецификация для AMD 8151
24888 Rev 3.03 - July 12, 2004
AMD-8151
TM
AGP Tunnel Data Sheet
15
The following are configuration spaces:
The IC does not claim configuration-register accesses to unimplemented functions within its devices (they are
forwarded to the other side of the tunnel). Accesses to unimplemented register locations within implemented
functions are claimed; such writes are ignored and reads always respond with all zeros.
forwarded to the other side of the tunnel). Accesses to unimplemented register locations within implemented
functions are claimed; such writes are ignored and reads always respond with all zeros.
The following are memory mapped spaces:
The following are register attributes found in the register descriptions.
5.2
AGP Device Configuration Registers
These registers are located in PCI configuration space, in the first device (device A), function 0. See section
5.1.2 for a description of the register naming convention.
5.1.2 for a description of the register naming convention.
AGP Vendor And Device ID Register
DevA:0x00
Default: 7454 1022h
Attribute: Read only.
Device
Function
Mnemonic Registers
"A"
0
DevA:0xXX AGP device header; link and AGP capabilities blocks
"B"
0
DevB:0xXX PCI-PCI bridge registers for AGP
Table 3: Configuration spaces.
Base address
register
Size
(bytes)
Mnemonic Registers
DevA:0x10
Variable
None
Graphic virtual memory aperture; minimum of 32 megabytes.
DevA:0xB8
4K
None
GART block in physical memory.
Table 4: Memory mapped address spaces.
Type
Description
Read or read-only
Capable of being read by software. Read-only implies that the register cannot be written to by
software.
software.
Write
Capable of being written by software.
Set by hardware
Register bit is set high by hardware.
Write once
After RESET#, these registers may be written to once. After being written, they become read only
until the next RESET# assertion. The write-once control is byte based. So, for example, software
may write each byte of a write-once DWORD as four individual transactions. As each byte is
written, that byte becomes read only.
until the next RESET# assertion. The write-once control is byte based. So, for example, software
may write each byte of a write-once DWORD as four individual transactions. As each byte is
written, that byte becomes read only.
Write 1 to clear
Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect.
Write 1 only
Software can set the bit high by writing a 1 to it. However subsequent writes of 0 will have no
effect. RESET# must be asserted in order to clear the bit.
effect. RESET# must be asserted in order to clear the bit.
Table 5: Register attributes.
Bits
Description
31:16 AGP device ID.
15:0
Vendor ID.