Справочник Пользователя для Cypress STK14D88
STK14D88
Document Number: 001-52037 Rev. **
Page 9 of 17
Hardware STORE Cycle
NO.
Symbols
Parameter
STK14D88
Unit
Notes
Standard
Alternate
Min
Max
31
t
DELAY
t
HLQZ
Hardware STORE to SRAM Disabled
1
70
µs
32
t
HLHX
Hardware STORE Pulse Width
15
ns
Figure 10. Hardware STORE Cycle
Soft Sequence Commands
NO.
Symbols
Parameter
STK14D88
Unit
Notes
Standard
Min
Max
33
t
SS
Soft Sequence Processing Time
70
µs
Figure 11. Software Sequence Commands
Notes
15. Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete.
16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
17. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
17. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.