Справочник Пользователя для Intel SE7520JR2
Intel® Server Board SE7520JR2
Functional Architecture
Revision 1.0
C78844-002
49
supports a maximum of 66MHz, the entire bus will throttle down to 66MHz to match the
supported frequency of that card. When populating add-in cards, the add-in cards must be
installed starting with the slot furthest from the baseboard. Ie) When using a three slot riser, a
single PCI-X add-in card must be installed in the top PCI slot. A second add-in card must be
installed in the middle slot, and so on. These population rules must be followed to maintain the
signal integrity of the bus.
supported frequency of that card. When populating add-in cards, the add-in cards must be
installed starting with the slot furthest from the baseboard. Ie) When using a three slot riser, a
single PCI-X add-in card must be installed in the top PCI slot. A second add-in card must be
installed in the middle slot, and so on. These population rules must be followed to maintain the
signal integrity of the bus.
The full-height riser slot implements Intel® Adaptive Slot Technology. This 280-pin connector is
capable of supporting riser cards that meet either the PCI-X or PCI-Express technology
specifications. As a PCI-X only bus, using a baseboard with integrated SCSI and passive riser
card, the P64-A bus can support bus speeds of up to 100MHz with up to two PCI-X 100MHz
cards installed. The bus speed will drop to 66MHz when three PCI-X 100MHz cards are
installed, or will match the card speed of the lowest speed card on the bus. Ie) If any of the add-
cards installed on the P64A bus supports a maximum of 66MHz, the entire bus will throttle down
to 66MHz to match the supported frequency of that card. When populating add-in cards, the
add-in cards must be installed starting with the slot furthest from the baseboard. Ie) When using
a three slot passive riser, a single PCI-X add-in card must be installed in the top PCI slot. A
second add-in card must be installed in the middle slot, and so on. These population rules must
be followed to maintain the signal integrity of the bus. On a baseboard with no integrated SCSI,
the P64-A bus is capable of supporting a bus speed of up to 133MHz when a 1U, single slot
riser card is used. I
capable of supporting riser cards that meet either the PCI-X or PCI-Express technology
specifications. As a PCI-X only bus, using a baseboard with integrated SCSI and passive riser
card, the P64-A bus can support bus speeds of up to 100MHz with up to two PCI-X 100MHz
cards installed. The bus speed will drop to 66MHz when three PCI-X 100MHz cards are
installed, or will match the card speed of the lowest speed card on the bus. Ie) If any of the add-
cards installed on the P64A bus supports a maximum of 66MHz, the entire bus will throttle down
to 66MHz to match the supported frequency of that card. When populating add-in cards, the
add-in cards must be installed starting with the slot furthest from the baseboard. Ie) When using
a three slot passive riser, a single PCI-X add-in card must be installed in the top PCI slot. A
second add-in card must be installed in the middle slot, and so on. These population rules must
be followed to maintain the signal integrity of the bus. On a baseboard with no integrated SCSI,
the P64-A bus is capable of supporting a bus speed of up to 133MHz when a 1U, single slot
riser card is used. I
Intel also makes available an active three slot PCI-X riser which utilizes a separate on board
PXH chip. This riser is capable of supporting up to two PCI-X 133MHz cards in addition to a
third PCI-X 100MHz card. If used in a baseboard with no on-board SCSI controller, the third
add-in slot can also operate at 133MHz.
PXH chip. This riser is capable of supporting up to two PCI-X 133MHz cards in addition to a
third PCI-X 100MHz card. If used in a baseboard with no on-board SCSI controller, the third
add-in slot can also operate at 133MHz.
When configured with a riser card supporting PCI-Express technology, the full height riser slot
can support riser cards that have either one x 8 PCI-Express card, or two x 4 PCI-Express
cards. Intel makes available a 1U single slot x8 riser card and a 2U three slot riser card which
provides two x8 connectors each supporting x4 data widths. The third slot is a PCI-X slot. Using
a baseboard configured with an integrated SCSI controller, the PCI-X add-in slot is capable of
supporting a bus speed of up to 100MHz. Installed in a baseboard with no integrated SCSI
controller, this PCI-X add-in slot is capable of supporting a bus speed of up to 133MHz.
can support riser cards that have either one x 8 PCI-Express card, or two x 4 PCI-Express
cards. Intel makes available a 1U single slot x8 riser card and a 2U three slot riser card which
provides two x8 connectors each supporting x4 data widths. The third slot is a PCI-X slot. Using
a baseboard configured with an integrated SCSI controller, the PCI-X add-in slot is capable of
supporting a bus speed of up to 100MHz. Installed in a baseboard with no integrated SCSI
controller, this PCI-X add-in slot is capable of supporting a bus speed of up to 133MHz.
3.4.1.5
PCI Scan Order
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local
Bus Specification. When a bridge device is located, the bus number is incremented in exception
of a bridge device in the chipsets. Scanning continues on the secondary side of the bridge until
all subordinate buses are defined. PCI bus numbers may change when PCI-PCI bridges are
added or removed. If a bridge is inserted in a PCI bus, all subsequent PCI bus numbers below
the current bus are increased by one.
Bus Specification. When a bridge device is located, the bus number is incremented in exception
of a bridge device in the chipsets. Scanning continues on the secondary side of the bridge until
all subordinate buses are defined. PCI bus numbers may change when PCI-PCI bridges are
added or removed. If a bridge is inserted in a PCI bus, all subsequent PCI bus numbers below
the current bus are increased by one.
3.4.1.6
PCI Bus Numbering
PCI configuration space protocol requires that all PCI buses in a system be assigned a bus
number. Bus numbers must be assigned in ascending order within hierarchical buses. Each PCI
bridge has registers containing its PCI bus number and subordinate PCI bus number, which
must be loaded by POST code. The subordinate PCI bus number is the bus number of the last
number. Bus numbers must be assigned in ascending order within hierarchical buses. Each PCI
bridge has registers containing its PCI bus number and subordinate PCI bus number, which
must be loaded by POST code. The subordinate PCI bus number is the bus number of the last