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DISK DRIVE OPERATION
SpinPoint V40 Product Manual
90
t
0
ADDR valid
(See note 1)
t
(See note 1)
t
1
t
2
t
9
t
2i
DIOR-/DIOW-
WRITE
DD(7:0)
(See note 2)
t
DD(7:0)
(See note 2)
t
3
t
4
READ
DD(7:0)
(See note 2)
t
DD(7:0)
(See note 2)
t
5
t
6
t
6z
IORDY
(See note 3,3-1)
t
(See note 3,3-1)
t
A
IORDY
(See note 3,3-2) t
(See note 3,3-2) t
C
t
RD
IORDY
(See note 3,3-3)
t
(See note 3,3-3)
t
B
t
C
NOTES
−
1 Device address consists of signals CS0-, CS1- and DA(2:0)
2 Data consists of DD(7:0).
3 The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the
2 Data consists of DD(7:0).
3 The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the
cycle is to be extended is made by the host after t
A
from the assertion of DIOR- or DIOW-. The
assertion and negation of IORDY are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t
A
, but causes IORDY to be asserted before t
A
. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3-3 Device negates IORDY before t
3-3 Device negates IORDY before t
A
. IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0)
for t
cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0)
for t
RD
before asserting IORDY.
4 DMACK – Shall remain negated during a register transfer.
Figure 6-1 Register transfer to/from device