Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
143
CPU Core Register Descriptions
33234H
5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR)
WB_LIP_MSR provides access to the WB stage linear instruction pointer.
5.5.2.40 C1/C0 Linear Instruction Pointer MSR (C1_C0_LIP_MSR)
C1_C0_LIP_MSR provides access to linear instruction pointers when the code segment was loaded.
MSR Address
00001365h
Type
RO
Reset Value
00000000_00000000h
WB_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WB_LIP
WB_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
RSVD
Reserved.
31:0
WB_LIP
WB Stage Linear Instruction Pointer.
MSR Address
00001366h
Type
RO
Reset Value
00000000_00000000h
C1_C0_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
C1_LIP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C0_LIP
C1_C0_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
C1_LIP
CS 1 Linear Instruction Pointer. Second most recent linear instruction point when code
segment was loaded.
segment was loaded.
31:0
C0_LIP
CS 0 Linear Instruction Pointer. Most recent linear instruction point when code seg-
ment was loaded.
ment was loaded.