Справочник Пользователя для AMD LX 900@1.5W
86
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.6
I/O Descriptors
I/O descriptors are ordered IOD_BM, IOD_SC. For example if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh =
IOD_BM[0] and MSR 100000E3h = IOD_SC[0].
IOD_BM[0] and MSR 100000E3h = IOD_SC[0].
4.2.6.1
IOD Base Mask Descriptors (IOD_BM)
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
GLIU0
IOD_BM[0:3]
MSR Address
100000E0h-100000E2h
Type
R/W
Reset Value
000000FF_FFF00000h
GLIU1
IOD_BM[0:3]
MSR Address
400000E0h-400000E2h
Type
R/W
Reset Value
000000FF_FFF00000h
IOD_BM[x] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IDID
IC
MP_BIZ
RSVD
IBASE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IBASE
IMASK
IOD_BM[x] Bit Descriptions
Bit
Name
Description
63:61
IDID
I/O Descriptor Destination ID. These bits define which Port to route the request to, if it
is a ‘hit’ based on the other settings in this register.
is a ‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
ICMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
Halt cycle.
59:40
RSVD
Reserved.
39:20
IBASE
Physical I/O Address Base. These bits form the matching value against which the
masked value of the physical address, bits [19:0] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
masked value of the physical address, bits [19:0] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
19:0
IMASK
Physical I/O Address Mask. These bits are used to mask address bits [31:12] for the
purposes of this ‘hit’ detection.
purposes of this ‘hit’ detection.