Справочник Пользователя для AMD LX 800@0.9W
132
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.24 SMM Header MSR (SMM_HDR_MSR)
The SMM_HDR_MSR provides access to the address register that controls where SMI data is written.
19
X
Executable Non-System Segment.
18
E/C
Expand Down Data Segment / Conforming Code Segment.
17
W/R
Writable Data Segment / Readable Code Segment.
16
A
Accessed Segment.
15:3
SELECTOR
Segment Selector.
2
TI
Descriptor Table Indicator (LDT/GDT).
1:0
RPL
Requestor Privilege Level.
MSR Address
0000132Bh
Type
R/W
Reset Value
00000000_00000000h
SMM_HDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SMM_HDR
Segment Selector/Flags MSR Bit Descriptions (Continued)
Bit
Name Description
SMM_HDR_MSR Bit Descriptions
Bit
Name
Description
63:32
RSVD
Reserved. Write as read.
31:0
SMM_HDR
SMM Header. Address that indicates where SMI data is written. SMI data is written at
lower addresses than SMM_HDR (negative offsets).
lower addresses than SMM_HDR (negative offsets).