Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
507
Video Input Port Register Descriptions
33234H
6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)
6.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)
VIP Memory Offset 70h
Type
Type
R/W
Reset Value
00000000h
VIP_FIFO_R_W_ADDR Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
FIFO_ADDRESS
VIP_FIFO_R_W_ADDR Bit Descriptions
Bit
Name
Description
31:9
RSVD
Reserved. Set to 0.
8:0
FIFO_ADDRESS
FIFO ADDRESS. FIFO address for which a FIFO read or write occurs. The data is writ-
ten/read via the FIFO Data register (VIP Memory Offset 74h). Note that the 256x64 bit
FIFO is mapped as a 512x32 bit memory.
ten/read via the FIFO Data register (VIP Memory Offset 74h). Note that the 256x64 bit
FIFO is mapped as a 512x32 bit memory.
VIP Memory Offset 74h
Type
Type
R/W
Reset Value
xxxxxxxxh
VIP_FIFO_DATA Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FIFO_DATA
VIP_FIFO_DATA Bit Descriptions
Bit
Name
Description
31:0
FIFO_DATA
FIFO Data. When the FF_R/W bit is set (VIP Memory Offset 04h[24] = 1), data written to
this register is stored in FIFO_ADDR (VIP Memory Offset 70h[7:0]). When the FF_R/W
bit is reset, data from the FIFO corresponding to the address in the FIFO_ADDR is
returned
this register is stored in FIFO_ADDR (VIP Memory Offset 70h[7:0]). When the FF_R/W
bit is reset, data from the FIFO corresponding to the address in the FIFO_ADDR is
returned