Справочник Пользователя для AMD LX 800@0.9W
62
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.3
Arbitration (ARB)
4.2.2.4
Asynchronous SMI (ASMI)
ASMI is a condensed version of the port ASMI signals. The MASK bits can be used to prevent a device from issuing an
ASMI. If the MASK = 1, the device’s ASMI is disabled.
ASMI. If the MASK = 1, the device’s ASMI is disabled.
MSR Address
GLIU0: 10000082h
GLIU1: 40000082h
GLIU1: 40000082h
Type
R/W
Reset Value
10000000_00000000h
ARB Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Q
U
A
C
K_EN
PIPE_DIS
RSVD
DA
C
K
_
E
N
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RSVD
ARB Bit Descriptions
Bit
Name
Description
63
QUACK_EN
Quadruple Acknowledge Enabled. Allow four acknowledgements in a row before
advancing round-robin arbitration. Only applies when arbitrating matching priorities.
advancing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
1: Enable.
62
PIPE_DIS
Pipelined Arbitration Disabled.
0: Pipelined arbitration enabled and GLIU is not limited to one outstanding transaction.
1: Limit the entire GLIU to one outstanding transaction.
1: Limit the entire GLIU to one outstanding transaction.
61
RSVD
Reserved.
60
DACK_EN
Double Acknowledge Enabled. Allow two acknowledgements in a row before advanc-
ing round-robin arbitration. Only applies when arbitrating matching priorities.
ing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
1: Enable.
59:0
RSVD
Reserved.
MSR Address
GLIU0: 10000083h
GLIU1: 40000083h
GLIU1: 40000083h
Type
R/W
Reset Value
00000000_00000000h
ASMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RSVD
AS
MI_
M
A
SK7
AS
MI_
M
A
SK6
AS
MI_
M
A
SK5
AS
MI_
M
A
SK4
AS
MI_
M
A
SK3
AS
MI_
M
A
SK2
AS
MI_
M
A
SK1
AS
MI_
M
A
SK0
ASMI_FLA
G
7
ASMI_FLA
G
6
ASMI_FLA
G
5
ASMI_FLA
G
4
ASMI_FLA
G
3
ASMI_FLA
G
2
ASMI_FLA
G
1
ASMI_FLA
G
0