Справочник Пользователя для AMD LX 800@0.9W
AMD Geode™ LX Processors Data Book
63
GLIU Register Descriptions
33234H
4.2.2.5
Asynchronous ERR (AERR)
AERR is a condensed version of the port ERR signals. The MASK bits can be used to prevent a device from issuing an
AERR. If the MASK = 1, the device’s AERR is disabled.
AERR. If the MASK = 1, the device’s AERR is disabled.
ASMI Bit Descriptions
Bit
Name
Description
63:16
RSVD
Reserved.
15
ASMI_MASK7
Asynchronous SMI Mask for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write 0 to
allow Port 7 to generate an ASMI. ASMI status is reported in bit 7.
allow Port 7 to generate an ASMI. ASMI status is reported in bit 7.
14
ASMI_MASK6
Asynchronous SMI Mask for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 0 to allow
Port 6 to generate an ASMI. ASMI status is reported in bit 6.
Port 6 to generate an ASMI. ASMI status is reported in bit 6.
13
ASMI_MASK5
Asynchronous SMI Mask for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 0 to allow Port 5
to generate an ASMI. ASMI status is reported in bit 5.
to generate an ASMI. ASMI status is reported in bit 5.
12
ASMI_MASK4
Asynchronous SMI Mask for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 0 to allow
Port 4 to generate an ASMI. ASMI status is reported in bit 4.
Port 4 to generate an ASMI. ASMI status is reported in bit 4.
11
ASMI_MASK3
Asynchronous SMI Mask for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 0 to
allow Port 3 to generate an ASMI. ASMI status is reported in bit 3.
allow Port 3 to generate an ASMI. ASMI status is reported in bit 3.
10
ASMI_MASK2
Asynchronous SMI Mask for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) Write 0
to allow Port 2 to generate an ASMI. ASMI status is reported in bit 2.
to allow Port 2 to generate an ASMI. ASMI status is reported in bit 2.
9
ASMI_MASK1
Asynchronous SMI Mask for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 0 to allow Port 1 to generate an ASMI. ASMI status is reported in bit 1.
Write 0 to allow Port 1 to generate an ASMI. ASMI status is reported in bit 1.
8
ASMI_MASK0
Asynchronous SMI Mask for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 0 to allow
Port 0 to generate an ASMI. ASMI status is reported in bit 0.
Port 0 to generate an ASMI. ASMI status is reported in bit 0.
7
ASMI_FLAG7
(RO)
(RO)
Asynchronous SMI Flag for Port 7 (Read Only). (GLIU0 = Not Used; GLIU1 = Not
Used.). If 1, this bit indicates that an ASMI was generated by Port 7. Cleared by source.
Used.). If 1, this bit indicates that an ASMI was generated by Port 7. Cleared by source.
6
ASMI_FLAG6
(RO)
(RO)
Asynchronous SMI Flag for Port 6 (Read Only). (GLIU0 = Not Used; GLIU1 = SB.) If 1,
this bit indicates that an ASMI was generated by Port 6. Cleared by source.
this bit indicates that an ASMI was generated by Port 6. Cleared by source.
5
ASMI_FLAG5
(RO)
(RO)
Asynchronous SMI Flag for Port 5 (Read Only). (GLIU0 = GP; GLIU1 = VIP.) If 1, this
bit indicates that an ASMI was generated by Port 5. Cleared by source.
bit indicates that an ASMI was generated by Port 5. Cleared by source.
4
ASMI_FLAG4
(RO)
(RO)
Asynchronous SMI Flag for Port 4 (Read Only). (GLIU0 = DC; GLIU1 = GLPCI.) If 1,
this bit indicates that an ASMI was generated by Port 4. Cleared by source.
this bit indicates that an ASMI was generated by Port 4. Cleared by source.
3
ASMI_FLAG3
(RO)
(RO)
Asynchronous SMI Flag for Port 3 (Read Only). (GLIU0 = CPU Core; GLIU1 = GLCP.)
If 1, this bit indicates that an ASMI was generated by Port37. Cleared by source.
If 1, this bit indicates that an ASMI was generated by Port37. Cleared by source.
2
ASMI_FLAG2
(RO)
(RO)
Asynchronous SMI Flag for Port 2 (Read Only). (GLIU0 = Interface to GLIU1; GLIU1 =
VP.) If 1, this bit indicates that an ASMI was generated by Port 2. Cleared by source.
VP.) If 1, this bit indicates that an ASMI was generated by Port 2. Cleared by source.
1
ASMI_FLAG1
(RO)
(RO)
Asynchronous SMI Flag for Port 1 (Read Only). (GLIU0 = GLMC; GLIU1 = Interface to
GLIU0.) If 1, this bit indicates that an ASMI was generated by Port 1. Cleared by source.
GLIU0.) If 1, this bit indicates that an ASMI was generated by Port 1. Cleared by source.
0
ASMI_FLAG0
(RO)
(RO)
Asynchronous SMI Flag for Port 0 (Read Only). (GLIU0 = GLIU; GLIU1 = GLIU.) If 1,
this bit indicates that an ASMI was generated by Port 0. Cleared by source.
this bit indicates that an ASMI was generated by Port 0. Cleared by source.
MSR Address
GLIU0: 10000084h
GLIU1: 40000084h
GLIU1: 40000084h
Type
R/W
Reset Value
00000000_00000000h