Справочник Пользователя для AMD LX 800@0.9W

33234H

The DMINT instruction saves portions of the processors state to the Debug Management Mode (DMM) header, alters the
processors state for DMM, enters DMM, and then calls the DMM mode handler. Below is the format of the DMM header.

All EFlags are returned to their reset values.

#UD

If current privilege level is not 0, or the DMM_INST_EN = 0 and if the processor is not in SMM and if the pro-

cessor is not in DMM.

Data address breakpoints on DMM header addresses that occur when executing the DMINT instruction are ignored.

The DMINT instruction clears the V, X, and H bits of the DMM header. DMINT sets the S bit of the DMM header. The
NEXT_IP failed of the DMM header will point to the instruction after the DMINT.

Same as an INT 1 instruction.

The ICEBP instruction generates a call to the Debug exception handler. It’s advantage over the INT 1 instruction is that it is
a single byte opcode.

The EFlags are pushed to the stack, and may then be modified before the debug exception handler is called. The EFlags
may be restored by the debug exception handler’s IRET.

Debuggers should not insert ICEBP instruction immediately after an instruction that alters the stack segment (MOV_SS).

DR6

-4

DR7

-8

XDR6

-C

XDR7

-10

SS FLAGS

SS SELECTOR

-14

G

B

0

Av

0

1

DPL

1

0

E

W

A

INDEX

TI

RPL

CS FLAGS

CS SELECTOR

-18

G

D

0

Av

0

1

DPL

1

1

C

f

R

A

INDEX

TI

RPL

CS BASE

-1C

0

CS LIMIT

-20

CURRENT_IP

-24

NEXT_IP

-28

CR0

-2C

EFLAGS

-30

0

c

w

0

c

r

0

V

X

0

H

S

0

0

0

-34

TEMP6

-38

AC TEMP0

-3C

F1

ICEBP

29+

Call Debug Exception Handler