Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333
Модели
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
124
Datasheet
5.2.34
EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A06–A07h
Default Value:
0000h
Access:
RW, RO
Size:
16 bits
See C0DRB0 register.
5.2.35
EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A08–A09h
Default Value:
0000h
Access:
RW
Size:
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
108h–109h
Ch0 Rank2, 3:
10Ah–10Bh
Ch1 Rank0, 1:
188h–189h
Ch1 Rank2, 3:
18Ah–18Bh
Bit
Access
Default
Value
Description
15:10
RO
000000b Reserved
9:0
RW
000h
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3):
Bit
Access
Default
Value
Description
15:8
RW
00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This register defines DRAM
pagesize/number-of-banks for rank1 for given channel.
pagesize/number-of-banks for rank1 for given channel.
7:0
RW
00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This register defines DRAM
pagesize/number-of-banks for rank0 for given channel.
pagesize/number-of-banks for rank0 for given channel.