Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

126

Datasheet

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: A1C–A1Fh

Default Value:

00000000h

Access:

RO, RW 

Size:

32 bits

EPD CYCTRK WRT ACT Status registers.

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: A20–A21h

Default Value:

0000h

Access:

RW, RO 

Size:

16 bits

EPD CYCTRK WRT WR Status registers.

31:21

RO

000h

Reserved 

20:17

RW

0000b

ACT to ACT Delayed (C0sd_cr_act_act[): This configuration register 
indicates the minimum allowed spacing (in DRAM clocks) between two ACT 
commands to the same rank.

16:13

RW

0000b

PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the minimum 
allowed spacing (in DRAM clocks) between the PRE and ACT commands to the 
same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed 
(C0sd_cr_preall_act):This configuration register indicates the minimum allowed 
spacing (in DRAM clocks) between the PRE-ALL and ACT commands to the same 
rank.

12:9

RO

0h

Reserved 

8:0

RW

0000000

00b

REF to ACT Delayed (C0sd_cr_rfsh_act): This configuration register 
indicates the minimum allowed spacing (in DRAM clocks) between REF and ACT 
commands to the same rank.

15:12

RW

0h

ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum 
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the 
same rank-bank

11:8

RW

0h

Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This field 
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE 
commands to the same rank.

7:4

RO

0h

Reserved 

3:0

RW

0h

Same Rank WRITE to READ Delay (C0sd_cr_rd_wr): This field indicates the 
minimum allowed spacing (in DRAM clocks) between the WRITE and READ 
commands to the same rank.