Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

Datasheet

127

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A22–A23h

Default Value:

0000h

Access:

RO, RW 

Size:

16 bits

BIOS Optimal Default

0h

EPD CYCTRK WRT ACT Status registers.

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A24–A26h

Default Value:

000000h

Access:

RW 

Size:

24 bits

BIOS Optimal Default

000h

EPD CYCTRK WRT RD Status registers.

15:9

RO

0s

Reserved 

8:0

RW

0000000

00b

Different Rank REF to REF Delayed (C0sd_cr_rfsh_rfsh): This 
configuration register indicates the minimum allowed spacing (in DRAM clocks) 
between two REF commands to different ranks.

23:23

RO

0h

Reserved

22:20

RW

000b

EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD): Configuration 
setting for Read command safe from the point of enabling the slave DLLs.

19:18

RO

0h

Reserved

17:14

RW

0h

Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the 
minimum allowed spacing (in DRAM clocks) between the ACT and READ 
commands to the same rank-bank

13:9

RW

00000b

Same Rank READ to WRITE Delayed (C0sd_cr_wrsr_rd): This field 
indicates the minimum allowed spacing (in DRAM clocks) between the READ and 
WRITE commands.

8:6

RO

0h

Reserved

5:3

RW

000b

Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field indicates 
the minimum allowed spacing (in DRAM clocks) between two READ commands to 
the same rank.

2:0

RO

0h

Reserved