Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

Datasheet

131

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: CD8h

Default Value:

00h

Access:

RW/L, RW, RS/WC 

Size:

8 bits

This register controls the operation of the thermal sensor.

Bits 7:1 of this register are reset to their defaults by MPWROK.

Bit 0 is reset to it's default by PLTRST#.

7

RW/L

0b

Thermal Sensor Enable (TSE): This bit enables power to the thermal sensor. 
Lockable via TCO bit [7].
0 = Disabled
1 = Enabled

6

RW

0b

Analog Hysteresis Control (AHC): This bit enables the analog hysteresis 
control to the thermal sensor. When enabled, about 1 degree of hysteresis is 
applied. This bit should normally be off in thermometer mode since the 
thermometer mode of the thermal sensor defeats the usefulness of analog 
hysteresis. 
0 = Hysteresis disabled
1 = Analog hysteresis enabled.

5:2

RW

0000b

Digital Hysteresis Amount (DHA): This bit determines whether no offset, 1 
LSB, 2... 15 is used for hysteresis for the trip points. 
0000 = Digital hysteresis disabled, no offset added to trip temperature
0001 = Offset is 1 LSB added to each trip temperature when tripped
...
0110 = ~3.0 °C (Recommended setting)
...
1110 = Added to each trip temperature when tripped
1111 = Added to each trip temperature when tripped

1

RW/L

0b

Thermal Sensor Comparator Select (TSCS): This bit multiplexes between 
the two analog comparator outputs. Normally Catastrophic is used. Lockable via 
TCO bit [7]. 
0 = Catastrophic
1 = Hot