Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333
Модели
P4X-UPE3210-316-6M1333
Datasheet
133
DRAM Controller Registers (D0:F0)
3:0
RW/L
0h
Thermometer Mode Enable and Rate (TE): If analog thermal sensor mode is
not enabled by setting these bits to 0000b, these bits enable the thermometer
mode functions and set the Thermometer controller rate.
When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog
sensor mode should be fully functional. In the analog sensor mode, the
Catastrophic trip is functional, and the Hot trip is functional at the offset below
the catastrophic programmed into TSC2[CHO]. The other trip points are not
functional in this mode.
When Thermometer mode is enabled, all the trip points (Catastrophic, Hot,
Aux0) will all operate using the programmed trip points and Thermometer mode
rate.
Note: When disabling the Thermometer mode while thermometer running, the
Thermometer mode controller will finish the current cycle.
Note: During boot, all other thermometer mode registers (except lock bits)
should be programmed appropriately before enabling the Thermometer Mode.
Clocks are memory clocks.
Note: Since prior MCHs counted the thermometer rate in terms of host clocks
rather than memory clocks, the clock count for each setting listed below has
been doubled from what is was on those MCHs. This should make the actual
thermometer rate approximately equivalent across products.
Lockable via TCO bit 7.
not enabled by setting these bits to 0000b, these bits enable the thermometer
mode functions and set the Thermometer controller rate.
When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog
sensor mode should be fully functional. In the analog sensor mode, the
Catastrophic trip is functional, and the Hot trip is functional at the offset below
the catastrophic programmed into TSC2[CHO]. The other trip points are not
functional in this mode.
When Thermometer mode is enabled, all the trip points (Catastrophic, Hot,
Aux0) will all operate using the programmed trip points and Thermometer mode
rate.
Note: When disabling the Thermometer mode while thermometer running, the
Thermometer mode controller will finish the current cycle.
Note: During boot, all other thermometer mode registers (except lock bits)
should be programmed appropriately before enabling the Thermometer Mode.
Clocks are memory clocks.
Note: Since prior MCHs counted the thermometer rate in terms of host clocks
rather than memory clocks, the clock count for each setting listed below has
been doubled from what is was on those MCHs. This should make the actual
thermometer rate approximately equivalent across products.
Lockable via TCO bit 7.
0000 = Thermometer mode disabled (i.e, analog sensor mode)
0001 = enabled, 512 clock mode
0010 = enabled, 1024 clock mode (normal Thermometer mode operation),
0001 = enabled, 512 clock mode
0010 = enabled, 1024 clock mode (normal Thermometer mode operation),
provides ~3.85 us settling time @ 266 MHz
provides ~3.08 us settling time @ 333 MHz
provides ~2.56 us settling time @ 400 MHz
provides ~3.08 us settling time @ 333 MHz
provides ~2.56 us settling time @ 400 MHz
0011 = enabled, 1536 clock mode
0100 = enabled, 2048 clock mode
0101 = enabled, 3072 clock mode
0110 = enabled, 4096 clock mode
0111 = enabled, 6144 clock mode
0100 = enabled, 2048 clock mode
0101 = enabled, 3072 clock mode
0110 = enabled, 4096 clock mode
0111 = enabled, 6144 clock mode
provides ~23.1 us settling time @ 266 MHz
provides ~18.5 us settling time @ 333 MHz
provides ~15.4 us settling time @ 400 MHz
provides ~18.5 us settling time @ 333 MHz
provides ~15.4 us settling time @ 400 MHz
all other permutations reserved
1111 = enabled, 4 clock mode (for testing digital logic)
1111 = enabled, 4 clock mode (for testing digital logic)
Bit
Access
Default
Value
Description