Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

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Datasheet

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 1h

Default Value:

00h

Access:

RW/V, RO/V 

Size:

8 bits

This implements the KT Interrupt Enable register. Host access to this address, depends 

on the state of the DLAB bit {KTLCR[7]). It must be "0" to access this register. The bits 

enable specific events to interrupt the Host. See bit specific definition.

Reset: Host System Reset or D3 -> D0 transition.

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 1h

Default Value:

00h

Access:

RW/V 

Size:

8 bits

Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this 

bit is 0, Host accesses the KTIER.

This is the standard Serial interface's Divisor Latch register's MSB. This register is only 

for software compatibility and does not affect performance of the hardware.

Reset: Host System Reset or D3->D0 transition.

7:4

RO/V

0h

Reserved 

3

RW/V

0b

MSR (IER2): When set, this bit enables bits in Modem Status register to cause 
an interrupt to host

2

RW/V

0b

LSR (IER1): When set, this bit enables bits in Receiver Line Status Register to 
cause an Interrupt to Host

1

RW/V

0b

THR (IER1): When set, this bit enables interrupt to be sent to Host when the 
tranmit Holding register is empty

0

RW/V

0b

DR (IER0): When set, Received Data Ready (or Receive FIFO Timeout) 
interrupts are enabled to be sent to Host.

7:0

RW/V

00h

Divisor Latch MSB (DLM): Implements the Divisor Latch MSB register of the 
Serial Interface.