Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

Datasheet

207

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 2h

Default Value:

01h

Access:

RO 

Size:

8 bits

The KT IIR register prioritizes the interrupts from the function into 4 levels and records 

them in the IIR_STAT field of the register. When Host accesses the IIR, hardware 

freezes all interrupts and provides the priority to the Host. Hardware continues to 

monitor the interrupts but does not change its current indication until the Host read is 

over. Table in the Host Interrupt Generation section shows the contents.

Reset: See specific Bit descriptions

7

RO

0b

FIFO Enable (FIEN1): This bit is connected by hardware to bit 0 in the FCR 
register. 
Reset: Host System Reset or D3->D0 transition

6

RO

0b

FIFO Enable (FIEN0): This bit is connected by hardware to bit 0 in the FCR 
register.
Reset: Host System Reset or D3->D0 transition

5:4

RO

00b

Reserved 

3:1

RO

000b

IIR STATUS (IIRSTS): These bits are asserted by the hardware according to 
the source of the interrupt and the priority level. Refer to the section on Host 
Interrupt Generation for a table of values.
Reset: ME system Reset

0

RO

1b

Interrupt Status (INTSTS): When "0" indicates pending interrupt to Host
When "1" indicates no pending interrupt to Host.
 Reset: Host system Reset or D3->D0 transition