Справочник Пользователя для Intel D425 AU80610006252AA

Datasheet 

 15 

Non-snooped accesses from DMI to this region are always sent to DRAM.  

0E0000H – 0E3FFFH 

WE  RE 

BIOS Extension 

0E4000H – 0E7FFFH 

WE  RE 

BIOS Extension 

0E8000H – 0EBFFFH 

WE  RE 

BIOS Extension 

0EC000H – 0EFFFFH 

WE  RE 

BIOS Extension 

This area is a single 64 KByte segment (000F_0000h – 000F_FFFFh). This segment 
can be assigned read and write attributes. It is by default (after reset) Read/Write 

disabled and cycles are forwarded to DMI Interface. By manipulating the Read/Write 
attributes, the IMC can “shadow” BIOS into the main DRAM. When disabled, this 

segment is not remapped. 

Non-snooped accesses from DMI to this region are always sent to DRAM.  

0F0000H – 0FFFFFH 

WE  RE 

BIOS Area 

The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM 
Memory Area. 

The IMC does not handle Implicit Write-Back (IWB) cycles targeting DMI. Since all 
memory residing on DMI should be set as non-cacheable, there will normally not be 

IWB cycles targeting DMI.  

However, DMI becomes the default target for CPU and DMI originated accesses to 
disabled segments of the PAM region. If the MTRRs covering the PAM regions are set 

to WB or RD it is possible to get IWB cycles targeting DMI. This may occur for CPU 

originated cycles (in a DP system) and for DMI originated cycles to disabled PAM 

regions. 

For example, say that a particular PAM region is set for “Read Disabled” and the MTRR 
associated with this region is set to WB. A DMI master generates a memory read 

targeting the PAM region. Since the PAM region is “Read Disabled” the default target 

for the Memory Read becomes DMI. The IWB associated with this cycle will cause the 
IMC to hang. 

This address range extends from 1 MB to the top of Low Usable physical memory that 
is permitted to be accessible by the IMC (as programmed in the TOLUD register). All