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Square wave rise/fall time (10 to 90%)

Low drive ........................................ 0.5 ns min,

2.5 ns max

High drive ....................................... 0.5 ns min,

2.5 ns max

Frequency range ..................................... DC to 105 MHz

Input impedance ..................................... 50

Ω, nominal, or 1 kΩ ±10%, 

|| 35 pF, software-selectable

Input coupling ........................................ DC

Voltage level .......................................... 0 to 5 V

Absolute maximum input voltage

1

......... ±5.25 V, max

Input threshold

Voltage level ................................... 0 to 4.3 V, software-selectable

Voltage resolution........................... 16.8 mV (8 bits)

Error ................................................ ±40 mV

Hysteresis ............................................... 50 mV

Asynchronous delay, t

pd

PFI <0..5> to 
PXI_TRIG <0..7> output ................ 19 to 26 ns, typical

PFI <0..5> to 
PXI_STAR <0..12> output ............. 10 to 19 ns, typical

Synchronized trigger 
input setup time, t

setup

2

........................... 16.5 ns, typical

Synchronized trigger 
input hold time, t

hold

2

.............................. –9.9 ns, typical

1   

Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for 

extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in 
the operational parts of the specifications is not implied.

2   

Relative to PXI_CLK10 at the backplane connector. When PLL is used to route CLKIN to PXI_CLK10_IN, CLKIN and 
PXI_CLK10 are phase locked with ±1 ns max phase difference. Refer to the 

 section of Chapter 3, 

, for more details.