Справочник Пользователя для IBM powerpc 750gx
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 304 of 377
gx_08.fm.(1.2)
March 27, 2006
(or only) data beat, the 750GX negates DBB but still considers the data beat active and waits for another
assertion of TA. DRTRY is ignored on write operations. TEA indicates a nonrecoverable bus error event.
Upon receiving a final (or only) termination condition, the 750GX always negates DBB for one cycle.
assertion of TA. DRTRY is ignored on write operations. TEA indicates a nonrecoverable bus error event.
Upon receiving a final (or only) termination condition, the 750GX always negates DBB for one cycle.
If DRTRY is asserted by the memory system to extend the last (or only) data beat past the negation of DBB,
the memory system should tristate the data bus on the clock after the final assertion of TA, even though it will
negate DRTRY on that clock. This is to prevent a potential momentary data-bus conflict if a write access
begins on the following cycle.
the memory system should tristate the data bus on the clock after the final assertion of TA, even though it will
negate DRTRY on that clock. This is to prevent a potential momentary data-bus conflict if a write access
begins on the following cycle.
The TEA signal is used to signal a nonrecoverable error during the data transaction. It can be asserted on
any cycle during DBB, or on the cycle after a qualified TA during a read operation, except when no-DRTRY
mode is selected (where no-DRTRY mode cancels checking the cycle after TA). The assertion of TEA termi-
nates the data tenure immediately even if in the middle of a burst. However, it does not prevent incorrect data
that has just been acknowledged with a TA from being written into the 750GX cache or to GPRs. The asser-
tion of TEA initiates either a machine-check exception or a checkstop condition based on the setting of the
MSR[ME] bit.
any cycle during DBB, or on the cycle after a qualified TA during a read operation, except when no-DRTRY
mode is selected (where no-DRTRY mode cancels checking the cycle after TA). The assertion of TEA termi-
nates the data tenure immediately even if in the middle of a burst. However, it does not prevent incorrect data
that has just been acknowledged with a TA from being written into the 750GX cache or to GPRs. The asser-
tion of TEA initiates either a machine-check exception or a checkstop condition based on the setting of the
MSR[ME] bit.
An assertion of ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the address
tenure associated with the data tenure in operation. If ARTRY is connected for the 750GX, the earliest allow-
able assertion of TA to the 750GX is directly dependent on the earliest possible assertion of ARTRY to the
750GX; see Section 8.3.3, Address Transfer Termination, on page 300.
tenure associated with the data tenure in operation. If ARTRY is connected for the 750GX, the earliest allow-
able assertion of TA to the 750GX is directly dependent on the earliest possible assertion of ARTRY to the
750GX; see Section 8.3.3, Address Transfer Termination, on page 300.
8.4.4.1 Normal Single-Beat Termination
Normal termination of a single-beat data read operation occurs when TA is asserted by a responding slave.
The TEA and DRTRY signals must remain negated during the transfer (see Figure 8-11).
The TEA and DRTRY signals must remain negated during the transfer (see Figure 8-11).
The DRTRY signal is not sampled during data writes, as shown in Figure 8-12.
Figure 8-11. Normal Single-Beat Read Termination
0
1
2
3
4
TS
qual DBG
DBB
data
ta
drtry
AACK