Справочник Пользователя для IBM powerpc 750gx
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_10.fm.(1.2)
March 27, 2006
March 27, 2006
Power and Thermal Management
Page 337 of 377
10.2.1 Power Management Modes
The following sections describe the characteristics of the 750GX’s power management modes, the require-
ments for entering and exiting the various modes, and the system capabilities provided by the 750GX while
the power management modes are active.
ments for entering and exiting the various modes, and the system capabilities provided by the 750GX while
the power management modes are active.
A power saving mode is activated by setting the power management enable bit in the Machine State Register
(MSR[POW]) and one of the three HID0 power saving mode bits which are listed in Table 10-2.
(MSR[POW]) and one of the three HID0 power saving mode bits which are listed in Table 10-2.
10.2.1.1 Full On Mode
Full on mode is selected when the POW bit in MSR is cleared. This is the default state following initialization
of a hard reset (HRESET). The 750GX is fully powered, and all functional units are operating at full processor
speed at all times.
of a hard reset (HRESET). The 750GX is fully powered, and all functional units are operating at full processor
speed at all times.
10.2.1.2 Doze Mode
Doze mode disables most functional units but maintains cache coherency by enabling the bus interface unit
and snooping. A snoop hit causes the 750GX to enable the data cache, copy the data back to memory,
disable the cache, and fully return to the doze state. Doze mode can be summarized as follows:
and snooping. A snoop hit causes the 750GX to enable the data cache, copy the data back to memory,
disable the cache, and fully return to the doze state. Doze mode can be summarized as follows:
• Most functional units are disabled.
• Data cache, L2 cache, bus snooping logic, and the time base/decrementer are still enabled.
• Doze mode is enabled with the following sequence:
1. Set the doze bit (HID0[8] = 1); clear the nap and sleep bits (HID0[9] and HID0[10] = 0).
2. 750GX enters doze mode after several processor clocks.
2. 750GX enters doze mode after several processor clocks.
• Several methods of returning to full-on mode:
– Assert INT, MCP, SMI, decrementer, performance-monitor, or thermal-management interrupts
– Assert hard reset or soft reset.
– Assert hard reset or soft reset.
• Transition to full-power state takes no more than a few processor cycles.
• Phase-locked loop (PLL) is required to be running and locked to the system clock (SYSCLK).
10.2.1.3 Nap Mode
The nap mode disables the 750GX but still maintains the PLL and the time base/decrementer. The time base
can be used to restore the 750GX to full-power state after a programmed amount of time. To maintain data
coherency, bus snooping is disabled for nap and sleep modes through a hardware handshake sequence
using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals. The 750GX asserts the QREQ
signal to indicate that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 750GX will enter the nap mode. If the system determines that a
bus snoop cycle is required, QACK is deasserted to the 750GX for at least eight bus clock cycles, and the
can be used to restore the 750GX to full-power state after a programmed amount of time. To maintain data
coherency, bus snooping is disabled for nap and sleep modes through a hardware handshake sequence
using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals. The 750GX asserts the QREQ
signal to indicate that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 750GX will enter the nap mode. If the system determines that a
bus snoop cycle is required, QACK is deasserted to the 750GX for at least eight bus clock cycles, and the
Table 10-2. HID0 Power Saving Mode Bit Settings
HID0 Bits
Power Saving Mode
8
Low-power doze
9
Low-power nap
10 Low-power
sleep