Справочник Пользователя для IBM powerpc 750gx
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umIX.fm.(1.2)
March 27, 2006
March 27, 2006
Index
Page 369 of 377
Index
A
AACK (address acknowledge) signal
,
ABB (address bus busy) signal
Address bus
address tenure
,
address transfer
An
,
APE
address transfer attribute
CI
,
GBL
TBST
TSIZn
,
TTn
,
,
WT
,
address transfer start
TS
address transfer termination
AACK
,
ARTRY
terminating address transfer
arbitration signals
,
,
bus parking
Address translation, see Memory management unit
Addressing modes
Addressing modes
,
Aligned data transfer
Alignment
data transfers
,
exception
misaligned accesses
,
rules
,
An (address bus) signals
,
APE (address parity error) signal
,
Arbitration, system bus
,
,
ARTRY (address retry) signal
,
B
BG (bus grant) signal
Block address translation
block address translation flow
definition
registers
description
,
initialization
,
selection of block address translation
,
Boundedly undefined, definition
,
BR (bus request) signal
,
,
Branch fall-through
,
Branch folding
Branch instructions
address calculation
,
condition register logical
list of instructions
system linkage
,
,
trap
Branch prediction
,
Branch processing unit
branch instruction timing
,
execution timing
,
latency, branch instructions
,
overview
Branch resolution
definition
resource requirements
,
BTIC (branch target instruction cache)
,
Burst data transfers
32-bit data bus
,
64-bit data bus
,
transfers with data delays, timing
,
Bus arbitration, see Data bus
Bus configurations
Bus configurations
,
Bus interface unit (BIU)
Bus transactions and L1 cache
Byte ordering
,
C
Cache
arbitration
block instructions
dcbi, data cache block invalidate
dcbt, data cache block touch
block, definition
,
bus interface unit
cache operations
load/store operations, processor initiated
operations
overview
,
cache unit overview
cache-inhibited accesses (I bit)
,
characteristics
,
coherency
description
,
overview
,
reaction to bus operations
control instructions
,
bus operations
,
data cache configuration
,
dcbf/dcbst execution
hit
icbi
,
instruction cache configuration
,
instruction cache throttling
integration
,
L1 cache and bus transactions