Справочник Пользователя для National Instruments AT E Series
Chapter 3
Hardware Overview
3-2
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Figure 3-2 shows the block diagram for the AT-MIO-64E-3.
Figure 3-2. AT-MIO-64E-3 Block Diagram
Timing
PFI / Trigger
I/O
Connector
3
RTSI Bus
AT
–
I/O
Channel
Digital I/O (8)
12-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
NI-PGIA
Gain
Amplifier
–
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Selection
Switches
Analog
Muxes
Voltage
REF
Calibration
DACs
Dither
Circuitry
Trigger
Analog
Trigger
Trigger
Circuitry
2
Trigger Level
DACs
6
Calibration
DACs
DAC0
DAC1
3
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Request
Bus
Interface
(32)
(32)
DAC
FIFO
8
Data (16)
AI Control
Data
(16)
Analog
Input
Control
EEPROM
Control
DMA
Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
Output
Control
8255
DIO
Control
Bus
Interface
IRQ
DMA
DMA
Data
Transceivers
AO Control
ADC
FIFO