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CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
DRAM Timing Settings
Item Help
HyperTransport Link Width Out Auto
HyperTransport Link Frequency 800MHz
Auto Configuration By SPD
X RAS Active Time (tRAS) 6 Bus Clock
X RAS Precharge Time (tRP) 3 Bus Clock
X RAS to CAS Delay (tRCD) 3 Bus Clock
X CAS Latency CL =2.5
HyperTransport Link Frequency 800MHz
Auto Configuration By SPD
X RAS Active Time (tRAS) 6 Bus Clock
X RAS Precharge Time (tRP) 3 Bus Clock
X RAS to CAS Delay (tRCD) 3 Bus Clock
X CAS Latency CL =2.5
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Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
RAS to CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T, 3T and 4T. (1T=1 Bus Clock)
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T, 3T and 4T. (1T=1 Bus Clock)
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
3-7 Integrated Peripherals