Техническая Спецификация для Intel P4500 CP80617004803AA
Модели
CP80617004803AA
Datasheet
77
Signal Description
6.7
DMI
6.8
PLL Signals
FDI_TX[7:4]
FDI_TX#[7:4]
Intel® Flexible Display Interface
Transmit Differential Pair - Pipe B
Transmit Differential Pair - Pipe B
O
FDI
FDI_FSYNC[1]
Intel® Flexible Display Interface Frame
Sync - Pipe B
Sync - Pipe B
I
CMOS
FDI_LSYNC[1]
Intel® Flexible Display Interface Line Sync
- Pipe B
- Pipe B
I
CMOS
FDI_INT
Intel® Flexible Display Interface Hot Plug
Interrupt
Interrupt
I
CMOS
Table 6-27.DMI - Processor to PCH Serial Interface
Signal Name
Description
Direction/Buffer
Type
DMI_RX[3:0]
DMI_RX#[3:0]
DMI Input from PCH: Direct Media
Interface receive differential pair.
Interface receive differential pair.
I
DMI
DMI_TX[3:0]
DMI_TX#[3:0]
DMI Output to PCH: Direct Media
Interface transmit differential pair.
Interface transmit differential pair.
O
DMI
Table 6-28.PLL Signals
Signal Name
Description
Direction/Buffer
Type
BCLK
BCLK#
Differential bus clock input to the processor
I
Diff Clk
BCLK_ITP
BCLK_ITP#
Buffered differential bus clock pair to ITP
O
Diff Clk
PEG_CLK
PEG_CLK#
Differential PCI Express Based
Graphics/DMI Clock In: These pins receive
a 100-MHz Serial Reference clock from the
external clock synthesizer. This clock is used
to generate the clocks necessary for the
support of PCI Express. This also is the
reference clock for Intel® FDI.
Graphics/DMI Clock In: These pins receive
a 100-MHz Serial Reference clock from the
external clock synthesizer. This clock is used
to generate the clocks necessary for the
support of PCI Express. This also is the
reference clock for Intel® FDI.
I
Diff Clk
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
Embedded Display Port PLL Differential
Clock In: With or without SSC -120 MHz.
Clock In: With or without SSC -120 MHz.
I
Diff Clk
Table 6-26.Intel® Flexible Display Interface (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type