Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
129
Processor Configuration Registers
2.6.48
LCAP2—Link Capabilities 2 Register
2.6.49
LCTL2—Link Control 2 Register
B/D/F/Type:
0/1/0–2/MMR
Address Offset:
CC–CFh
Reset Value:
0000000Eh
Access:
RO-V
Size:
32 bits
BIOS Optimal Default
0000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:8
RO
0h
Reserved (RSVD)
7:1
RO-V
07h
Uncore
Supported Link Speeds Vector (SLSV)
This field indicates the supported Link speed(s) of the associated
This field indicates the supported Link speed(s) of the associated
Port. For each bit, a value of 1b indicates that the corresponding
Link speed is supported; otherwise, the Link speed is not
supported.
Bit definitions are:
Bit 1 = 2.5 GT/s
Bit 2 = 5.0 GT/s
Bit 3 = 8.0 GT/s
Bits 7:4 = Reserved
Multi-Function devices associated with an Upstream Port must
Bit definitions are:
Bit 1 = 2.5 GT/s
Bit 2 = 5.0 GT/s
Bit 3 = 8.0 GT/s
Bits 7:4 = Reserved
Multi-Function devices associated with an Upstream Port must
report the same value in this field for all Functions.
DMI does not support this control register since it is Gen3
DMI does not support this control register since it is Gen3
register.
0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
D0–D1h
Reset Value:
0003h
Access:
RWS, RWS-V
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:11
RO
0h
Reserved (RSVD)
10
RWS
0b
Powergood
Enter Modified Compliance (entermodcompliance)
When this bit is set to 1b, the device transmits modified
When this bit is set to 1b, the device transmits modified
compliance pattern if the LTSSM enters Polling.Compliance
state.
Components that support only the 2.5 GT/s speed are
Components that support only the 2.5 GT/s speed are
permitted to hardwire this bit to 0b.
Reset Value of this field is 0b.
Reset Value of this field is 0b.
9:7
RO
0h
Reserved (RSVD)