Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
131
Processor Configuration Registers
2.6.50
LSTS2—Link Status 2 Register
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
D2–D3h
Reset Value:
0000h
Access:
RO-V, RW1C
Size:
16 bits
BIOS Optimal Default
000h
Bit
Access
Reset
Value
RST/
PWR
Description
15:6
RO
0h
Reserved (RSVD)
5
RW1C
0b
Uncore
Link Equalization Request (LNKEQREQ)
This bit is set by hardware to request the Link equalization
This bit is set by hardware to request the Link equalization
process to be performed on the Link. Refer to PCIe Specification,
Sections 4.2.3 and 4.2.6.4.2 for details.
The Reset Value of this bit is 0b.
The Reset Value of this bit is 0b.
4
RO-V
0b
Uncore
Equalization Phase 3 Successful (EQPH3SUCC)
When set to 1b, this bit indicates that Phase 3 of the Transmitter
When set to 1b, this bit indicates that Phase 3 of the Transmitter
Equalization procedure has successfully completed. Details of the
Transmitter Equalization process and when this bit needs to be
set to 1b is provided in PCIe Specification, Section 4.2.6.4.2.
The Reset Value of this bit is 0b.
The Reset Value of this bit is 0b.
3
RO-V
0b
Uncore
Equalization Phase 2 Successful (EQPH2SUCC)
When set to 1b, this bit indicates that Phase 2 of the Transmitter
When set to 1b, this bit indicates that Phase 2 of the Transmitter
Equalization procedure has successfully completed. Details of the
Transmitter Equalization process and when this bit needs to be
set to 1b is provided in PCIe specification Section 4.2.6.4.2.
The Reset Value of this bit is 0b.
The Reset Value of this bit is 0b.
2
RO-V
0b
Uncore
Equalization Phase 1 Successful (EQPH1SUCC)
When set to 1b, this bit indicates that Phase 1 of the Transmitter
When set to 1b, this bit indicates that Phase 1 of the Transmitter
Equalization procedure has successfully completed. Details of the
Transmitter Equalization process and when this bit needs to be
set to 1b is provided in PCIe specification Section 4.2.6.4.2.
The Reset Value of this bit is 0b.
The Reset Value of this bit is 0b.
1
RO-V
0b
Uncore
Equalization Complete (EQCOMPLETE)
When set to 1b, this bit indicates that the Transmitter
When set to 1b, this bit indicates that the Transmitter
Equalization procedure has completed. Details of the Transmitter
Equalization process and when this bit needs to be set to 1b is
provided in PCIe specification Section 4.2.6.4.2.
The Reset Value of this bit is 0b.
The Reset Value of this bit is 0b.
0
RO-V
0b
Uncore
Current De-emphasis Level (CURDELVL)
When the Link is operating at 5 GT/s speed, this reflects the level
When the Link is operating at 5 GT/s speed, this reflects the level
of de-emphasis.
1 = -3.5 dB
0 = -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
1 = -3.5 dB
0 = -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.