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286

Datasheet, Volume 2

This register configures the base address and size of the invalidation queue. This 
register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as 
not supported in the Extended Capability register.

This register reports completion status of invalidation wait descriptor with Interrupt 
Flag (IF) set. 

This register is treated as RsvdZ by implementations reporting Queued Invalidation 
(QI) as not supported in the Extended Capability register.

63:39

RO

0h

38:12

RW-L

0000000h

Uncore

Invalidation Queue Base Address (IQA) 
This field points to the base of 4 KB aligned invalidation request 

queue. Hardware ignores and does not implement bits 63:HAW, 

where HAW is the host address width.
Reads of this field return the value that was last programmed to 

it. 

11:3

RO

0h

2:0

RW-L

0h

Uncore

Queue Size (QS) 
This field specifies the size of the invalidation request queue. A 

value of X in this field indicates an invalidation request queue of 

(2^X) 4 KB pages. The number of entries in the invalidation 

queue is 2^(X + 8). 

31:1

RO

0h

0

RW1CS

0b

Powergood

Invalidation Wait Descriptor Complete (IWC) 
This bit indicates completion of Invalidation Wait Descriptor 

with Interrupt Flag (IF) field set. Hardware implementations not 

supporting queued invalidations implement this field as RsvdZ.