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Datasheet, Volume 2

This register specifies the Invalidation Event interrupt message data.

This register is treated as RsvdZ by implementations reporting Queued Invalidation 
(QI) as not supported in the Extended Capability register.

This register specifies the Invalidation Event Interrupt message address.

This register is treated as RsvdZ by implementations reporting Queued Invalidation 
(QI) as not supported in the Extended Capability register.

31:16

RW-L

0000h

Uncore

Extended Interrupt Message Data (EIMD) 
This field is valid only for implementations supporting 32-bit 

interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data 

treat this field as Rsvd. 

15:0

RW-L

0000h

Uncore

Interrupt Message data (IMD)
Data value in the interrupt request. 

31:2

RW-L

00000000

h

Uncore

Message address (MA) 
When fault events are enabled, the contents of this register 

specify the DWord-aligned address (bits 31:2) for the interrupt 

request. 

1:0

RO

0h