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Datasheet, Volume 2

289

Processor Configuration Registers 

This register specifies the Invalidation Event interrupt message upper address.

This register provides the base address of Interrupt remapping table. This register is 
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not 
supported in the Extended Capability register.

31:0

RW-L

00000000h

Uncore

Message Upper Address (MUA) 
Hardware implementations supporting Queued Invalidations and 

Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations 

or Extended Interrupt Mode may treat this field as RsvdZ.

63:39

RO

0h

38:12

RW-L

0000000h

Uncore

Interrupt Remapping Table Address (IRTA)
This field points to the base of 4 KB aligned interrupt remapping 

table.
Hardware ignores and does not implement bits 63:HAW, where 

HAW is the host address width.
Reads of this field returns value that was last programmed to it. 

11:4

RO

0h

3:0

RW-L

0h

Uncore

Size (S)
This field specifies the size of the interrupt remapping table. The 

number of entries in the interrupt remapping table is 2^(X+1), 

where X is the value programmed in this field.