Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
335
Processor Configuration Registers
2.21.21 IQA_REG—Invalidation Queue Address Register
This register configures the base address and size of the invalidation queue. This
register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as
not supported in the Extended Capability register.
register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as
not supported in the Extended Capability register.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
90–97h
Reset Value:
0000000000000000h
Access:
RW-L
Size:
64 bits
BIOS Optimal Default
000000000h
Bit
Access
Reset
Value
RST/
PWR
Description
63:39
RO
0h
Reserved (RSVD)
38:12
RW-L
0000000h
Uncore
Invalidation Queue Base Address (IQA)
This field points to the base of 4 KB aligned invalidation request
This field points to the base of 4 KB aligned invalidation request
queue. Hardware ignores and does not implement bits 63:HAW,
where HAW is the host address width.
Reads of this field return the value that was last programmed to
Reads of this field return the value that was last programmed to
it.
11:3
RO
0h
Reserved (RSVD)
2:0
RW-L
0h
Uncore
Queue Size (QS)
This field specifies the size of the invalidation request queue. A
This field specifies the size of the invalidation request queue. A
value of X in this field indicates an invalidation request queue of
(2^X) 4 KB pages. The number of entries in the invalidation
queue is 2^(X + 8).