Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
337
Processor Configuration Registers
2.21.24 IEDATA_REG—Invalidation Event Data Register
This register specifies the Invalidation Event interrupt message data.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
(QI) as not supported in the Extended Capability register.
30
RO-V
0b
Uncore
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt
Hardware sets the IP field whenever it detects an interrupt
condition. Interrupt condition is defined as:
• An Invalidation Wait Descriptor with Interrupt Flag (IF) field
set completed, setting the IWC field in the Invalidation
Completion Status register.
• If the IWC field in the Invalidation Completion Status register
was already set at the time of setting this field, it is not
treated as a new interrupt condition.
The IP field is kept set by hardware while the interrupt message
is held pending. The interrupt message could be held pending
due to interrupt mask (IM field) being set, or due to other
transient hardware conditions. The IP field is cleared by hardware
as soon as the interrupt message pending condition is serviced.
This could be due to either:
• Hardware issuing the interrupt message due to either change
in the transient hardware condition that caused interrupt
message to be held pending or due to software clearing the
IM field.
• Software servicing the IWC field in the Invalidation
Completion Status register.
29:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
A0–A3h
Reset Value:
80000000h
Access:
RW-L, RO-V
Size:
32 bits
BIOS Optimal Default
00000000h
Bit
Access
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
A4–A7h
Reset Value:
00000000h
Access:
RW-L
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:16
RW-L
0000h
Uncore
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
Hardware implementations supporting only 16-bit interrupt data
treat this field as Rsvd.
15:0
RW-L
0000h
Uncore
Interrupt Message data (IMD)
Data value in the interrupt request.
Data value in the interrupt request.