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Datasheet, Volume 2
339
Processor Configuration Registers
2.21.27 IRTA_REG—Interrupt Remapping Table Address Register
This register provides the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
B8–BFh
Reset Value:
0000000000000000h
Access:
RW-L
Size:
64 bits
BIOS Optimal Default
00000000h
Bit
Access
Reset
Value
RST/
PWR
Description
63:39
RO
0h
Reserved (RSVD)
38:12
RW-L
0000000h
Uncore
Interrupt Remapping Table Address (IRTA)
This field points to the base of 4 KB aligned interrupt remapping
This field points to the base of 4 KB aligned interrupt remapping
table.
Hardware ignores and does not implement bits 63:HAW, where
Hardware ignores and does not implement bits 63:HAW, where
HAW is the host address width.
Reads of this field returns value that was last programmed to it.
Reads of this field returns value that was last programmed to it.
11:4
RO
0h
Reserved (RSVD)
3:0
RW-L
0h
Uncore
Size (S)
This field specifies the size of the interrupt remapping table. The
This field specifies the size of the interrupt remapping table. The
number of entries in the interrupt remapping table is 2^(X+1),
where X is the value programmed in this field.