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Datasheet, Volume 2

This register contains the revision number of the processor root port. These bits are 
read only and writes to this register have no effect.

This register identifies the basic function of the device, a more specific sub-class, and a 
register-specific programming interface.

7:0

RO-FW

0h

Uncore

Revision Identification Number (RID)
This is an 8-bit value that indicates the revision identification 

number for the root port. Refer to the Mobile 3rd Generation 

 Core™ Processor Family Specification Update for the value 

of the RID register. 

23:16

RO

06h

Uncore

Base Class Code (BCC) 
This field indicates the base class code for this device. This code 

has the value 06h indicating a Bridge device. 

15:8

RO

04h

Uncore

Sub-Class Code (SUBCC) 
This field indicates the sub-class code for this device. The code is 

04h indicating a PCI to PCI Bridge. 

7:0

RO

00h

Uncore

Programming Interface (PI) 
This field indicates the programming interface of this device. This 

value does not specify a particular register set layout and 

provides no practical use for this device. 

7:0

RW

00h

Uncore

Cache Line Size (CLS)
Implemented by PCI Express devices as a read-write field for 

legacy compatibility purposes but has no impact on any PCI 

Express device functionality.