Техническая Спецификация для Texas Instruments DDC11XEVM-PDK - DDC11xEVM-PDK Evaluation Module DDC11XEVM-PDK DDC11XEVM-PDK
Модели
DDC11XEVM-PDK
T
=
INT
Q
I
IN
IN(max)
V
I
REF
IN(max)
T
C
C
INT
INT
=
C
=
INT
Q
V
0.1V
IN
REF
-
www.ti.com
DDC112EVM Hardware Description
Assuming a 10MHz system clock (pin 10 of the DUT), the relationship between the integration time, input
current, and input charge is summarized in
current, and input charge is summarized in
through
(1)
(2)
where
•
T
INT
= integration time in ms
•
Q
IN
= input charge in coloumbs
•
I
IN
= input current in amperes
(3)
The dual switched integrators of the A/D converter use a differential input topology, with the noninverting
input internally tied to VREF. This architecture allows the digitizer to operate from a single supply. Before
the beginning of each integration, the integrator is reset to VREF. Additionally, the offset, offset drift, noise,
and kT/C errors are corrected at that time. A low-noise voltage reference of 4.096V (nominal) provides the
best performance from the DDC112. The reference that is designed for the DDC112EVM DUT board is
implemented with a LM4040 (4.1V reference), a low-pass R/C filter, and a single-supply operational
amplifier (U3). The operational amplifier is loaded with multiple capacitors in an effort to further reduce
reference noise and ripple.
input internally tied to VREF. This architecture allows the digitizer to operate from a single supply. Before
the beginning of each integration, the integrator is reset to VREF. Additionally, the offset, offset drift, noise,
and kT/C errors are corrected at that time. A low-noise voltage reference of 4.096V (nominal) provides the
best performance from the DDC112. The reference that is designed for the DDC112EVM DUT board is
implemented with a LM4040 (4.1V reference), a low-pass R/C filter, and a single-supply operational
amplifier (U3). The operational amplifier is loaded with multiple capacitors in an effort to further reduce
reference noise and ripple.
A digital filter in the DDC112 passes a low-noise, high-resolution digital output to the serial I/O register.
Because the serial I/O register is independent of the DDC112 conversion process, the output of multiple
DDC112 units can be connected together in series to minimize interconnections.
Because the serial I/O register is independent of the DDC112 conversion process, the output of multiple
DDC112 units can be connected together in series to minimize interconnections.
The DDC112 integrates on one side of the dual switched integrator while it digitizes the other side (as
illustrated in
illustrated in
). In the event that the integration time is less than the amount of time required to
digitize Channel 1 and Channel 2, the DDC112 changes to a non-continuous mode. In this mode, the
integration is not continuous and the device appears to skip integrations. The limiting factor in these
situations is the time required to digitize the signals (Channel 1 and Channel 2).
integration is not continuous and the device appears to skip integrations. The limiting factor in these
situations is the time required to digitize the signals (Channel 1 and Channel 2).
3
DDC112EVM Hardware Description
The DDC112EVM is a device-under-test (DUT) board that contains one DDC112 device to be tested, data
buffers, 4.1V reference, decoupling capacitors, sockets for optional input circuits, sockets for optional
external gain configurations, and an analog breadboard area (see
buffers, 4.1V reference, decoupling capacitors, sockets for optional input circuits, sockets for optional
external gain configurations, and an analog breadboard area (see
for layout artwork and
appended schematic).
The PC interface board (DDCMB) and the DUT board are separate to minimize digital noise effects on the
DDC112 unit being tested, as well as to allow for other DUT boards to be used (for example, a board with
multiple converters). Digital buffers are installed at both ends of the interface to improve the isolation
between the boards.
DDC112 unit being tested, as well as to allow for other DUT boards to be used (for example, a board with
multiple converters). Digital buffers are installed at both ends of the interface to improve the isolation
between the boards.
The DDC112EVM DUT board is carefully laid out to ensure low-noise evaluations. Note that all the digital
pins are located on one end of the DDC112U with the analog pins on the other. Be careful to keep the
digital activity as far away from the analog pins as possible. In particular, pins 9 through 17 of the
DDC112U have higher digital activity than the others, and should be shielded from the analog functions.
The digital return lines are carefully separated on the DDC112EVM DUT board. The additional ground
plane shields on the top and bottom of the DDC112EVM DUT board are installed with the board to ensure
that low-noise tests are possible. During operation, the lid of the DDC112EVM DUT board should be
closed.
pins are located on one end of the DDC112U with the analog pins on the other. Be careful to keep the
digital activity as far away from the analog pins as possible. In particular, pins 9 through 17 of the
DDC112U have higher digital activity than the others, and should be shielded from the analog functions.
The digital return lines are carefully separated on the DDC112EVM DUT board. The additional ground
plane shields on the top and bottom of the DDC112EVM DUT board are installed with the board to ensure
that low-noise tests are possible. During operation, the lid of the DDC112EVM DUT board should be
closed.
5
SLAU234A – October 2007 – Revised July 2010
DDC11xEVM-PDK User's Guide
Copyright © 2007–2010, Texas Instruments Incorporated