Техническая Спецификация для Texas Instruments DDC11XEVM-PDK - DDC11xEVM-PDK Evaluation Module DDC11XEVM-PDK DDC11XEVM-PDK
Модели
DDC11XEVM-PDK
DDC112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Digital I/O
and
Digital Power
Digital I/O
and
Digital Power
Shield
external
caps when
used
Analog
Ground
Ground
Analog
Power
Shield
external
caps when
used
Analog
Ground
Analog
Ground
IN1
IN2
Analog
Ground
DDC112EVM Hardware Description
www.ti.com
Proper grounding and shielding practices should be taken into consideration when designing the circuit
layout for the DDC112. In the event that the application cannot tolerate the additional shields of the
DDC112EVM DUT board, an alternative layout is shown in
layout for the DDC112. In the event that the application cannot tolerate the additional shields of the
DDC112EVM DUT board, an alternative layout is shown in
, where a PC ground plane is placed
around the inputs of the DDC112 (pins 1 and 28). This shield helps minimize coupled noise into the input
pins. Additionally, the pins that are used for the external integration capacitors (pins 3, 4, 5, 6, 23, 24, 25,
and 26) should be guarded by a ground plane when the external capacitors are used.
pins. Additionally, the pins that are used for the external integration capacitors (pins 3, 4, 5, 6, 23, 24, 25,
and 26) should be guarded by a ground plane when the external capacitors are used.
The digital and analog planes are not separate on this demonstration fixture because of the low level of
digital activity on the board. Regardless of the power-supply strategy, the bypass capacitors should be as
close to the device as possible.
digital activity on the board. Regardless of the power-supply strategy, the bypass capacitors should be as
close to the device as possible.
Figure 4. Recommended Shield for DDC112 Layout Design
3.1
Reference Circuit
The 4.096V reference that has been installed on the DDC112EVM DUT board has been carefully selected
because of its low-noise performance. The LM4040-4.1 provides a 4.096V (nominal) reference. At the
reference output, a single pole (3.157Hz) low-pass filter is inserted in the reference signal path. This filter
is then followed by an amplifier configured as a buffer. The output of the amplifier has been loaded with
20.1
because of its low-noise performance. The LM4040-4.1 provides a 4.096V (nominal) reference. At the
reference output, a single pole (3.157Hz) low-pass filter is inserted in the reference signal path. This filter
is then followed by an amplifier configured as a buffer. The output of the amplifier has been loaded with
20.1
m
F of capacitance. This value of capacitance was derived through experimentation. The voltage
reference circuit described above has been found to enable the DDC112U to perform optimally.
To evaluate alternative reference circuits, use jumper JP1 to connect an external reference source through
the BNC connector, J5, or a user-designed reference circuit from the breadboard.
the BNC connector, J5, or a user-designed reference circuit from the breadboard.
shows the
jumper settings for JP1.
6
DDC11xEVM-PDK User's Guide
SLAU234A – October 2007 – Revised July 2010
Copyright © 2007–2010, Texas Instruments Incorporated