Техническая Спецификация для Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X
Модели
DK-TM4C129X
Table 21-1. I2C Signals (212BGA) (continued)
Description
Buffer Type
Pin Type
Pin Mux / Pin
Assignment
Pin Number
Pin Name
I
2
C module 6 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
not be configured as open drain.
OD
I/O
PA6 (2)
PB6 (2)
V5
F2
F2
I2C6SCL
I
2
C module 6 data.
OD
I/O
PA7 (2)
PB7 (2)
R7
F1
I2C6SDA
I
2
C module 7 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
not be configured as open drain.
OD
I/O
PA4 (2)
PD0 (2)
V4
C2
C2
I2C7SCL
I
2
C module 7 data.
OD
I/O
PA5 (2)
PD1 (2)
W4
C1
I2C7SDA
I
2
C module 8 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
not be configured as open drain.
OD
I/O
PA2 (2)
PD2 (2)
T6
D2
I2C8SCL
I
2
C module 8 data.
OD
I/O
PA3 (2)
PD3 (2)
U5
D1
D1
I2C8SDA
I
2
C module 9 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
not be configured as open drain.
OD
I/O
PA0 (2)
PE6 (2)
V3
A7
A7
I2C9SCL
I
2
C module 9 data.
OD
I/O
PA1 (2)
PE7 (2)
W3
B7
I2C9SDA
21.3
Functional Description
Each I
2
C module is comprised of both master and slave functions and is identified by a unique
address. A master-initiated communication generates the clock signal, SCL. For proper operation,
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I
2
C bus configuration is
shown in Figure 21-2. Refer to the I2C-bus specification and user manual to determine the size of
the pull-ups needed for proper operation.
the pull-ups needed for proper operation.
2
C timing diagrams.
Figure 21-2. I
2
C Bus Configuration
RPUP
Tiva™
Microcontroller
I2CSCL
I2CSDA
RPUP
3rd Party Device
with I
2
C Interface
SCL
SDA
I
2
C Bus
SCL
SDA
SCL
SDA
3rd Party Device
with I
2
C Interface
21.3.1
I
2
C Bus Functional Overview
The I
2
C bus uses only two signals: SDA and SCL, named
I2CSDA
and
I2CSCL
on TM4C129XNCZAD
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
line. The bus is considered idle when both lines are High.
1427
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller