Техническая Спецификация для Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1
Модели
DM240013-1
2011 Microchip Technology Inc.
DS31037B-page 61
PIC24F16KL402 FAMILY
TABLE 7-1:
RESET FLAG BIT OPERATION
7.1
Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in
device Reset is chosen, as shown in
. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
For more information, see
selected according to the oscillator Configuration bits.
For more information, see
.
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
bit 3
SLEEP:
Wake-up from Sleep Flag bit
1
= Device has been in Sleep mode
0
= Device has not been in Sleep mode
bit 2
IDLE:
Wake-up from Idle Flag bit
1
= Device has been in Idle mode
0
= Device has not been in Idle mode
bit 1
BOR:
Brown-out Reset Flag bit
1
= A Brown-out Reset has occurred (the BOR is also set after a POR)
0
= A Brown-out Reset has not occurred
bit 0
POR:
Power-on Reset Flag bit
1
= A Power-up Reset has occurred
0
= A Power-up Reset has not occurred
Flag Bit
Setting Event
Clearing Event
TRAPR (RCON<15>)
Trap Conflict Event
POR
IOPUWR (RCON<14>)
Illegal Opcode or Uninitialized W Register Access
POR
CM (RCON<9>)
Configuration Mismatch Reset
POR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET
Instruction
POR
WDTO (RCON<4>)
WDT Time-out
PWRSAV
Instruction, POR
SLEEP (RCON<3>)
PWRSAV #SLEEP
Instruction
POR
IDLE (RCON<2>)
PWRSAV #IDLE
Instruction
POR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note:
All Reset flag bits may be set or cleared by the user software.
REGISTER 7-1:
RCON: RESET CONTROL REGISTER
(
1
)
(CONTINUED)
Note 1:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
cause a device Reset.
2:
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
SWDTEN bit setting.
3:
The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>).
When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.
When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.
Reset Type
Clock Source Determinant
POR
FNOSC Configuration bits
(FNOSC<10:8>)
(FNOSC<10:8>)
BOR
MCLR
COSC Control bits
(OSCCON<14:12>)
(OSCCON<14:12>)
WDTO
SWR