Техническая Спецификация для Microchip Technology MA330026
2011-2014 Microchip Technology Inc.
DS70000652F-page 129
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 3
CF: Clock Fail Detect bit (read/clear by application)
1
= FSCM has detected a clock failure
0
= FSCM has not detected a clock failure
bit 2
Unimplemented: Read as ‘0’
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit
1
= Enables secondary oscillator
0
= Disables secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1
= Requests oscillator switch to selection specified by the NOSC<2:0> bits
0
= Oscillator switch is complete
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
(
1
)
(CONTINUED)
Note 1:
Writes to this register require an unlock sequence. Refer to “Oscillator (Part VI)” (DS70644) in the
“dsPIC33/PIC24 Family Reference Manual” for details.
“dsPIC33/PIC24 Family Reference Manual” for details.
2:
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.