Техническая Спецификация для Microchip Technology MA330026
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 130
2011-2014 Microchip Technology Inc.
REGISTER 8-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
ROI
DOZE2
DOZE1
)
DOZE0
DOZEN
(
)
FRCDIV2
FRCDIV1
FRCDIV0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1
= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0
= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
,
)
111
= F
CY
/128
110
= F
CY
/64
101
= F
CY
/32
100
= F
CY
/16
011
= F
CY
/8 (default)
010
= F
CY
/4
001
= F
CY
/2
000
= F
CY
/1
bit 11
DOZEN: DOZE Mode Enable bit
)
1
= DOZE<2:0> bits field specifies the ratio between the peripheral clocks and the processor clocks
0
= Processor clock/peripheral clock ratio is forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111
= FRC divide-by-256
110
= FRC divide-by-64
101
= FRC divide-by-32
100
= FRC divide-by-16
011
= FRC divide-by-8
010
= FRC divide-by-4
001
= FRC divide-by-2
000
= FRC divide-by-1 (default)
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
This bit is cleared when the ROI bit is set and an interrupt occurs.
2:
If DOZEN = 1, writes to DOZE<2:0> are ignored.
3:
If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.