Техническая Спецификация для Microchip Technology DM183037
PIC18F97J94 FAMILY
DS30575A-page 466
2012 Microchip Technology Inc.
22.5.4
MONITORING
SAMPLE/CONVERSION STATUS
SAMPLE/CONVERSION STATUS
The DONE bit (ADCON1L<0>) indicates the conver-
sion state of the A/D. Generally, when the SAMP bit
clears, indicating the end of sampling, the DONE bit is
automatically cleared to indicate the start of conver-
sion. If SAMP is '0' while DONE is '1', the A/D is in an
inactive state.
In some operational modes, the SAMP bit may also
invoke and terminate sampling. In these modes, the
DONE bit cannot be used to terminate conversions in
progress.
sion state of the A/D. Generally, when the SAMP bit
clears, indicating the end of sampling, the DONE bit is
automatically cleared to indicate the start of conver-
sion. If SAMP is '0' while DONE is '1', the A/D is in an
inactive state.
In some operational modes, the SAMP bit may also
invoke and terminate sampling. In these modes, the
DONE bit cannot be used to terminate conversions in
progress.
22.5.5
GENERATING A/D INTERRUPTS
The SMPI<4:0> bits (ADCON2L<6:2>) control the
generation of the A/D Interrupt Flag, ADIF. The A/D
Interrupt Flag is set after the number of sample/conver-
sion sequences is specified by the SMPIx bits, after the
start of sampling, and continues to recur after that
number of samples. The value specified by the SMPIx
bits also corresponds to the number of data samples in
the buffer, up to the maximum of 16. To enable the
interrupt, it is necessary to set the A/D Interrupt Enable
bit, ADIE.
If auto-scan is enabled (ADCON5<7> = 1), interrupt
generation is controlled by the ASINTMDx bits
(ADCON5H<1:0>). For more information, refer to
generation of the A/D Interrupt Flag, ADIF. The A/D
Interrupt Flag is set after the number of sample/conver-
sion sequences is specified by the SMPIx bits, after the
start of sampling, and continues to recur after that
number of samples. The value specified by the SMPIx
bits also corresponds to the number of data samples in
the buffer, up to the maximum of 16. To enable the
interrupt, it is necessary to set the A/D Interrupt Enable
bit, ADIE.
If auto-scan is enabled (ADCON5<7> = 1), interrupt
generation is controlled by the ASINTMDx bits
(ADCON5H<1:0>). For more information, refer to
22.5.6
ABORTING A CONVERSION
Clearing the ADON bit during a conversion will abort
the current conversion. The A/D results buffer will not
be updated with the partially completed A/D conversion
sample; that is, the corresponding ADCBUF buffer
location will continue to contain the value of the last
completed conversion (or the last value written to the
buffer).
the current conversion. The A/D results buffer will not
be updated with the partially completed A/D conversion
sample; that is, the corresponding ADCBUF buffer
location will continue to contain the value of the last
completed conversion (or the last value written to the
buffer).
22.5.7
OFFSET CALIBRATION
The module provides a simple calibration method to
offset the effects of internal device noise. While not
always necessary, this may be helpful in situations
where weak analog signals are being converted.
Calibration is performed by using the OFFCAL bit
(ADCON2H<4>). This disconnects the S/H amplifier
entirely from any inputs. With the OFFCAL bit set, a
single reference conversion is performed. The results
of this conversion are value added by internal device
noise. This result can be stored by the application, then
used as an offset value for future conversions.
offset the effects of internal device noise. While not
always necessary, this may be helpful in situations
where weak analog signals are being converted.
Calibration is performed by using the OFFCAL bit
(ADCON2H<4>). This disconnects the S/H amplifier
entirely from any inputs. With the OFFCAL bit set, a
single reference conversion is performed. The results
of this conversion are value added by internal device
noise. This result can be stored by the application, then
used as an offset value for future conversions.
22.6
A/D Results Buffer
As conversions are completed, the module writes the
results of the conversions into the A/D result buffer.
This buffer is a RAM array of fixed word size, accessed
through the SFR space. The size of the buffer is deter-
mined by the number of external analog input channels
on the device, allowing one word for each channel.
Depending on the device, additional buffer space may
be provided for one or more internal analog channels
(e.g., band gap sources). The number of buffer
addresses is always even and always at least equal to
the number of external channels.
User software may attempt to read each A/D conver-
sion result as it is generated; however, this might
consume too much CPU time. Generally, to minimize
software overhead, the module will fill the buffer with
results and then generate an interrupt when the buffer
is filled.
results of the conversions into the A/D result buffer.
This buffer is a RAM array of fixed word size, accessed
through the SFR space. The size of the buffer is deter-
mined by the number of external analog input channels
on the device, allowing one word for each channel.
Depending on the device, additional buffer space may
be provided for one or more internal analog channels
(e.g., band gap sources). The number of buffer
addresses is always even and always at least equal to
the number of external channels.
User software may attempt to read each A/D conver-
sion result as it is generated; however, this might
consume too much CPU time. Generally, to minimize
software overhead, the module will fill the buffer with
results and then generate an interrupt when the buffer
is filled.
22.6.1
NUMBER OF CONVERSIONS PER
INTERRUPT
INTERRUPT
The SMPI<4:0> bits select how many A/D conversions
will take place before the CPU is interrupted. This can
vary from 1 to 16 samples per interrupt. The A/D
Converter module always starts writing its conversion
results at the beginning of the buffer, after each
interrupt. For example, if SMPI<4:0> = 00000, the
conversion results will always be written to the
ADCBUF0. In this example, no other buffer locations
would be used, since only one sequence per interrupt
is specified.
will take place before the CPU is interrupted. This can
vary from 1 to 16 samples per interrupt. The A/D
Converter module always starts writing its conversion
results at the beginning of the buffer, after each
interrupt. For example, if SMPI<4:0> = 00000, the
conversion results will always be written to the
ADCBUF0. In this example, no other buffer locations
would be used, since only one sequence per interrupt
is specified.
22.6.2
BUFFER FILL MODES
The results buffer can be configured to operate in either
of two modes: a standard FIFO mode, compatible with
the earlier 10-bit A/D module (default), or a Channel
Indexed mode. The Fill mode is selected by the
BUFREGEN bit (ADCON2H<3>).
of two modes: a standard FIFO mode, compatible with
the earlier 10-bit A/D module (default), or a Channel
Indexed mode. The Fill mode is selected by the
BUFREGEN bit (ADCON2H<3>).
22.6.2.1
FIFO Modes
When BUFREGEN = 0, the results buffer operates in
FIFO mode. The first conversion results, after initiating
conversions, is written to the first available buffer
address. Subsequent conversions are written to the
next sequential buffer location, continuing until the
process is interrupted. If allowed to continue without
interrupts, the module would fill each location and then
wrap around to the first address, continuing the
process.
FIFO mode. The first conversion results, after initiating
conversions, is written to the first available buffer
address. Subsequent conversions are written to the
next sequential buffer location, continuing until the
process is interrupted. If allowed to continue without
interrupts, the module would fill each location and then
wrap around to the first address, continuing the
process.
Note:
This section describes buffer operation in
Legacy mode (AD1CON5<3:2> = 00).
Buffer operation is different when the
Compare Only or Compare and Save
modes are used with the Threshold Detect
feature. For more information, see
Legacy mode (AD1CON5<3:2> = 00).
Buffer operation is different when the
Compare Only or Compare and Save
modes are used with the Threshold Detect
feature. For more information, see
.