Техническая Спецификация для Microchip Technology DM183037
2012 Microchip Technology Inc.
DS30575A-page 71
PIC18F97J94 FAMILY
4.4
Deep Sleep Modes
The Deep Sleep modes puts the device into its lowest
power consumption states without requiring the use of
external switches to remove power from the device.
There are two modes available: Deep Sleep mode and
Retention Deep Sleep mode.
During both Deep Sleep modes, the power to the
microcontroller core is removed to reduce leakage
current. Therefore, most peripherals and functions of
the microcontroller become unavailable during Deep
Sleep. However, a few specific peripherals and func-
tions are powered directly from the V
power consumption states without requiring the use of
external switches to remove power from the device.
There are two modes available: Deep Sleep mode and
Retention Deep Sleep mode.
During both Deep Sleep modes, the power to the
microcontroller core is removed to reduce leakage
current. Therefore, most peripherals and functions of
the microcontroller become unavailable during Deep
Sleep. However, a few specific peripherals and func-
tions are powered directly from the V
DD
supply rail of
the microcontroller, and therefore, can continue to
function in Deep Sleep. In addition, four data memory
locations, DSGPR0, DSGPR1, DSGPR2 and
DSGPR3, are preserved for context information after
an exit from Deep Sleep.
Deep Sleep has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events in Deep Sleep mode. The DSBOR and DSWDT
are independent of the standard BOR and WDT used
with other power-managed modes (Run, Idle and
Sleep).
Entering Deep Sleep mode clears the Deep Sleep
Wake-up Source Registers (DSWAKEL and
DSWAKEH). If enabled, the Real-Time Clock and
Calendar (RTCC) continues to operate uninterrupted.
When a wake-up event occurs in Deep Sleep mode (by
Reset, RTCC alarm, External Interrupt (INT0) or
DSWDT), the device will exit Deep Sleep mode and
re-arm a Power-on Reset (POR). When the device is
released from Reset, code execution will resume at the
Reset vector.
function in Deep Sleep. In addition, four data memory
locations, DSGPR0, DSGPR1, DSGPR2 and
DSGPR3, are preserved for context information after
an exit from Deep Sleep.
Deep Sleep has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events in Deep Sleep mode. The DSBOR and DSWDT
are independent of the standard BOR and WDT used
with other power-managed modes (Run, Idle and
Sleep).
Entering Deep Sleep mode clears the Deep Sleep
Wake-up Source Registers (DSWAKEL and
DSWAKEH). If enabled, the Real-Time Clock and
Calendar (RTCC) continues to operate uninterrupted.
When a wake-up event occurs in Deep Sleep mode (by
Reset, RTCC alarm, External Interrupt (INT0) or
DSWDT), the device will exit Deep Sleep mode and
re-arm a Power-on Reset (POR). When the device is
released from Reset, code execution will resume at the
Reset vector.
4.4.1
RETENTION DEEP SLEEP MODE
In Retention Deep Sleep, the retention regulator is
enabled, which allows the data RAM to retain data
while all other systems are powered down. This also
allows the device to return to code execution where it
left off, instead of going through a POR-like Reset.
As a trade-off, Retention Deep Sleep mode has greater
power consumption than Deep Sleep. However, it
offers the lowest level of power consumption of the
power-saving modes that still allows a direct return to
code execution.
Retention Deep Sleep is controlled by the SRETEN bit
(RCON4<4>) and the RETEN Configuration bit, as
described in
enabled, which allows the data RAM to retain data
while all other systems are powered down. This also
allows the device to return to code execution where it
left off, instead of going through a POR-like Reset.
As a trade-off, Retention Deep Sleep mode has greater
power consumption than Deep Sleep. However, it
offers the lowest level of power consumption of the
power-saving modes that still allows a direct return to
code execution.
Retention Deep Sleep is controlled by the SRETEN bit
(RCON4<4>) and the RETEN Configuration bit, as
described in
4.4.2
ENTERING DEEP SLEEP MODES
Deep Sleep modes are entered by:
• Setting the DSEN bit (DSCONH<7>)
• Executing the SLEEP instruction
To enter Retention Deep Sleep, the SRETEN bit must
also be set prior to setting the DSEN bit (
• Setting the DSEN bit (DSCONH<7>)
• Executing the SLEEP instruction
To enter Retention Deep Sleep, the SRETEN bit must
also be set prior to setting the DSEN bit (
In order to minimize the possibility of inadvertently
entering Deep Sleep, the DSEN bit must be set by two
separate write operations. To enter Deep Sleep, the
SLEEP instruction must be executed after setting the
DSEN bit (i.e., the next instruction). If DSEN is not set
when Sleep is executed, the device will enter a Sleep
mode instead.
entering Deep Sleep, the DSEN bit must be set by two
separate write operations. To enter Deep Sleep, the
SLEEP instruction must be executed after setting the
DSEN bit (i.e., the next instruction). If DSEN is not set
when Sleep is executed, the device will enter a Sleep
mode instead.
4.4.3
DEEP SLEEP WAKE-UP SOURCES
The device can be awakened from Deep Sleep modes
by any of the following:
• MCLR
• POR
• RTCC Alarm
• INT0 Interrupt
• DSWDT Event
After waking from Deep Sleep mode, the device per-
forms a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the
DPSLP bit (RCON4<2>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DPSLP bit must be
manually cleared by the software.
The software can determine the wake-up event source
by reading the DSWAKE registers. These registers are
cleared automatically when entering Deep Sleep
mode, so software should read these registers after
exiting Deep Sleep mode or before re-enabling this
mode.
by any of the following:
• MCLR
• POR
• RTCC Alarm
• INT0 Interrupt
• DSWDT Event
After waking from Deep Sleep mode, the device per-
forms a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the
DPSLP bit (RCON4<2>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DPSLP bit must be
manually cleared by the software.
The software can determine the wake-up event source
by reading the DSWAKE registers. These registers are
cleared automatically when entering Deep Sleep
mode, so software should read these registers after
exiting Deep Sleep mode or before re-enabling this
mode.
4.4.4
CLOCK SELECTION ON WAKE-UP
FROM DEEP SLEEP MODE
FROM DEEP SLEEP MODE
For Deep Sleep mode, the processor will restart with
the default oscillator source, selected with the FOSCx
Configuration bits. On wake-up from Deep Sleep, a
POR is generated internally, hence, the system resets
to its POR state with the exception of the RCONx,
DSCONH/L and DSGPRx registers.
For Retention Deep Sleep, the processor restarts with
the same clock source that was selected before enter-
ing Retention Deep Sleep mode. Wake-up is similar to
that of Sleep and Retention Sleep modes.
the default oscillator source, selected with the FOSCx
Configuration bits. On wake-up from Deep Sleep, a
POR is generated internally, hence, the system resets
to its POR state with the exception of the RCONx,
DSCONH/L and DSGPRx registers.
For Retention Deep Sleep, the processor restarts with
the same clock source that was selected before enter-
ing Retention Deep Sleep mode. Wake-up is similar to
that of Sleep and Retention Sleep modes.