Техническая Спецификация для Microchip Technology DM183037
PIC18F97J94 FAMILY
DS30575A-page 72
2012 Microchip Technology Inc.
4.4.5
SAVING CONTEXT DATA WITH THE
DSGPRx REGISTERS
DSGPRx REGISTERS
As exiting Deep Sleep mode causes a POR, most
Special Function Registers (SFRs) reset to their default
POR values. In addition, because the core power is not
supplied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode. Applications which
require critical data to be saved prior to Deep Sleep may
use the Deep Sleep General Purpose registers,
DSGPR0, DSGPR1, DSGPR2 and DSGPR3. Unlike
other SFRs, the contents of these registers are pre-
served while the device is in Deep Sleep mode. After
exiting Deep Sleep, software can restore the data by
reading the registers and clearing the RELEASE bit
(DSCONL<0>).
Any data stored in the DSGPRx registers must be writ-
ten twice. Like other Deep Sleep control features, the
write operations do not need to be sequential. However,
back-to-back writes are a recommended programming
practice.
Since the contents of data RAM are maintained in
Retention Deep Sleep, the use of the DSGPRx registers
to store critical data is not necessary in this mode.
Special Function Registers (SFRs) reset to their default
POR values. In addition, because the core power is not
supplied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode. Applications which
require critical data to be saved prior to Deep Sleep may
use the Deep Sleep General Purpose registers,
DSGPR0, DSGPR1, DSGPR2 and DSGPR3. Unlike
other SFRs, the contents of these registers are pre-
served while the device is in Deep Sleep mode. After
exiting Deep Sleep, software can restore the data by
reading the registers and clearing the RELEASE bit
(DSCONL<0>).
Any data stored in the DSGPRx registers must be writ-
ten twice. Like other Deep Sleep control features, the
write operations do not need to be sequential. However,
back-to-back writes are a recommended programming
practice.
Since the contents of data RAM are maintained in
Retention Deep Sleep, the use of the DSGPRx registers
to store critical data is not necessary in this mode.
4.4.6
I/O PINS DURING DEEP SLEEP
During Deep Sleep, general purpose I/O pins retain
their previous states. Pins that are configured as inputs
(TRIS bit is set), prior to entry into Deep Sleep, remain
high-impedance during Deep Sleep.
Pins that are configured as outputs (TRIS bit is clear),
prior to entry into Deep Sleep, will remain as output pins
during Deep Sleep. While in this mode, they will drive the
output level determined by their corresponding LAT bit at
the time of entry into Deep Sleep.
Once the device wakes back up, all I/O pins will continue
to maintain their previous states, even after the device
has finished the POR sequence and is executing applica-
tion code again. Pins configured as inputs during Deep
Sleep will remain high-impedance and pins configured as
outputs will continue to drive their previous value. After
waking up, the TRIS and LAT registers will be reset. If
firmware modifies the TRIS and LAT values for the I/O
pins, they will not immediately go to the newly configured
states. Once the firmware clears the RELEASE bit
(DSCONL<0>), the I/O pins are “released”. This
causes the I/O pins to take the states configured by
their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR event occurs during Deep Sleep (or V
their previous states. Pins that are configured as inputs
(TRIS bit is set), prior to entry into Deep Sleep, remain
high-impedance during Deep Sleep.
Pins that are configured as outputs (TRIS bit is clear),
prior to entry into Deep Sleep, will remain as output pins
during Deep Sleep. While in this mode, they will drive the
output level determined by their corresponding LAT bit at
the time of entry into Deep Sleep.
Once the device wakes back up, all I/O pins will continue
to maintain their previous states, even after the device
has finished the POR sequence and is executing applica-
tion code again. Pins configured as inputs during Deep
Sleep will remain high-impedance and pins configured as
outputs will continue to drive their previous value. After
waking up, the TRIS and LAT registers will be reset. If
firmware modifies the TRIS and LAT values for the I/O
pins, they will not immediately go to the newly configured
states. Once the firmware clears the RELEASE bit
(DSCONL<0>), the I/O pins are “released”. This
causes the I/O pins to take the states configured by
their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR event occurs during Deep Sleep (or V
DD
is
hard-cycled to V
SS
), the I/O pins will be immediately
released, similar to clearing the RELEASE bit. All
previous state information will be lost, including the
general purpose DSGPR0, DSGPR1, DSGPR2 and
DSGPR3 contents. DSGPRx register contents will be
maintained if the V
previous state information will be lost, including the
general purpose DSGPR0, DSGPR1, DSGPR2 and
DSGPR3 contents. DSGPRx register contents will be
maintained if the V
BAT
pin is powered.
If a MCLR Reset event occurs during Deep Sleep, the
I/O pins will also be released automatically, but in this
case, the DSGPR0, DSGPR1, DSGPR2 and DSGPR3
contents will remain valid.
In case of MCLR Reset and all other Deep Sleep wake-up
cases, application firmware needs to clear the RELEASE
bit (DSCONL<0>) in order to reconfigure the I/O pins.
I/O pins will also be released automatically, but in this
case, the DSGPR0, DSGPR1, DSGPR2 and DSGPR3
contents will remain valid.
In case of MCLR Reset and all other Deep Sleep wake-up
cases, application firmware needs to clear the RELEASE
bit (DSCONL<0>) in order to reconfigure the I/O pins.
4.4.7
DEEP SLEEP WATCHDOG TIMER
(DSWDT)
(DSWDT)
Deep Sleep has its dedicated WDT (DSWDT). It is
enabled through the DSWDTEN Configuration bit. The
DSWDT is equipped with a postscaler for time-outs of
2.1 ms to 25.7 days, configurable through the Configura-
tion bits, DSWDTPS<4:0>. Entering Deep Sleep mode
automatically clears the DSWDT.
The DSWDT also has a configurable reference clock
source for selecting the LPRC or SOSC. The reference
clock source is configured through the DSWDTOSC
Configuration bit.
Under certain circumstances, it is possible for the DSWDT
clock source to be off when entering Deep Sleep mode. In
this case, the clock source is turned on automatically (if
DSWDT is enabled), without the need for software inter-
vention. However, this can cause a delay in the start of the
DSWDT counters. In order to avoid this delay, when using
SOSC as a clock source, the application can activate
SOSC prior to entering Deep Sleep mode.
enabled through the DSWDTEN Configuration bit. The
DSWDT is equipped with a postscaler for time-outs of
2.1 ms to 25.7 days, configurable through the Configura-
tion bits, DSWDTPS<4:0>. Entering Deep Sleep mode
automatically clears the DSWDT.
The DSWDT also has a configurable reference clock
source for selecting the LPRC or SOSC. The reference
clock source is configured through the DSWDTOSC
Configuration bit.
Under certain circumstances, it is possible for the DSWDT
clock source to be off when entering Deep Sleep mode. In
this case, the clock source is turned on automatically (if
DSWDT is enabled), without the need for software inter-
vention. However, this can cause a delay in the start of the
DSWDT counters. In order to avoid this delay, when using
SOSC as a clock source, the application can activate
SOSC prior to entering Deep Sleep mode.
4.4.8
DEEP SLEEP LOW-POWER
BROWN-OUT RESET
BROWN-OUT RESET
Devices with a Deep Sleep Power-Saving mode also
have a dedicated BOR for Deep Sleep modes (DSBOR).
It has a trip point range of 1.7V-2.3V nominal and is
enabled through the DSBOREN (CONFIG7L<3>)
Configuration bit.
When the device enters a Deep Sleep mode and
receives a DSBOR event, the device will not wake-up
and will remain in the Deep Sleep mode. When a valid
wake-up event occurs and causes the device to exit
Deep Sleep mode, software can determine if a DSBOR
event occurred during Deep Sleep mode by reading the
BOR (DSWAKEL<6>) status bit.
have a dedicated BOR for Deep Sleep modes (DSBOR).
It has a trip point range of 1.7V-2.3V nominal and is
enabled through the DSBOREN (CONFIG7L<3>)
Configuration bit.
When the device enters a Deep Sleep mode and
receives a DSBOR event, the device will not wake-up
and will remain in the Deep Sleep mode. When a valid
wake-up event occurs and causes the device to exit
Deep Sleep mode, software can determine if a DSBOR
event occurred during Deep Sleep mode by reading the
BOR (DSWAKEL<6>) status bit.
4.4.9
RTCC AND DEEP SLEEP
The RTCC can operate uninterrupted during Deep
Sleep modes. It can wake-up the device from Deep
Sleep by configuring an alarm. The RTCC clock source
is configured with the RTCC Clock Select bits,
RTCCLKSEL<1:0>. The available reference clock
sources are the LPRC and SOSC. If the LPRC is used,
the RTCC accuracy will directly depend on the LPRC
tolerance.
If the RTCC is not required, Deep Sleep mode with the
RTCC disabled, affords the lowest power consumption
of any of the instruction-based power-saving modes.
Sleep modes. It can wake-up the device from Deep
Sleep by configuring an alarm. The RTCC clock source
is configured with the RTCC Clock Select bits,
RTCCLKSEL<1:0>. The available reference clock
sources are the LPRC and SOSC. If the LPRC is used,
the RTCC accuracy will directly depend on the LPRC
tolerance.
If the RTCC is not required, Deep Sleep mode with the
RTCC disabled, affords the lowest power consumption
of any of the instruction-based power-saving modes.