Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO

Freescale Semiconductor

34

This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC 
synchronization, and JTAG/EOnCE interfaces. 

V

DD

, V

SS

 and V

DDA

, V

SSA

 are the primary power supply pins for the devices. This voltage source supplies power to all on-chip 

peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated 
lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators.

Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage. 
In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10 

F tantalum capacitor, to provide bulk charge 

storage for the overall system and a 0.1 

F ceramic bypass capacitor located as near to the device power pins as practical to 

suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. 

V

DDA

 

and V

SSA

are the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and 

CMP modules. A 0.1 

F ceramic bypass capacitor should be located as near to the device V

DDA

 

and V

SSA

 pins as practical to 

suppress high-frequency noise. V

DDA

 

and V

SSA

 are also the voltage reference high and voltage reference low inputs, 

respectively, for the ADC module.

Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and 
status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules 
are disabled and I/O pins are initially configured as the reset status shown in 

. The 56F8006/56F8002 has the following 

sources for reset:

•

Power-on reset (POR)

•

Partial power down reset (PPD)

•

Low-voltage detect (LVD)

•

External pin reset (EXTR)

•

Computer operating properly loss of reference reset (COP_LOR)

•

Computer operating properly time-out reset (COP_CPU)

•

Software Reset (SWR)

Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM). 

The external pin reset function is shared with an GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled 
following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When 
enabled as the RESET pin, an internal pullup device is automatically enabled.

The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an 
external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz.

The features of OCCS module include:

•

Ability to power down the internal relaxation oscillator or crystal oscillator

•

Ability to put the internal relaxation oscillator into standby mode

•

Ability to power down the PLL