Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO

Freescale Semiconductor

35

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Provides a 3X system clock that operates at three times the system clock to PWM, timer, and SCI modules

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Safety shutdown feature is available if the PLL reference clock is lost

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Can be driven from an external clock source

The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal 
oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the 
SIM. The SIM is responsible for further dividing these frequencies by two, which ensures a 50% duty cycle in the system clock 
output. For detail, see the OCCS chapter in the MC56F8006 Peripheral Reference Manual.

An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It 
is optimized for accuracy and programmability while providing several power-saving configurations that accommodate 
different operating conditions. The internal relaxation oscillator has little temperature and voltage variability. To optimize 
power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state.

During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). 
Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a 
changeover between internal and external clock sources is required at power-on, ensure that the clock source is not switched 
until the desired external clock source is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally 
adjusted to within + 0.078% of 8 MHz by trimming an internal capacitor. Bits 0–9 of the OSCTL (oscillator control) register 
allow you to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or 
subtracted changes the output frequency by about 0.078% of 8 MHz, allowing incremental adjustment until the desired 
frequency accuracy is achieved.

The center frequency of the internal oscillator is calibrated at the factory to 8 MHz and the TRIM value is stored in the flash 
information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read 
the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the MC56F8006 Peripheral Reference 
Manual.

The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the frequency range, 
specified for the external crystal, of 32.768 kHz (Typ) or 1–16 MHz. A ceramic resonator can be substituted for the 1–16 MHz 
range. When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 4 MHz to 8 MHz 
(recommend 8 MHz) range to achieve optimized PLL performance. Oscillator circuits are shown in 

.

 Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the 

component values required to provide maximum stability and reliable start-up. The load capacitance values used in the 
oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted 
as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. When using 
low-frequency, low-power mode, the only external component is the crystal itself. In the other oscillator modes, load capacitors 
(C

x

, C

y

) and feedback resistor (R

F

) are required. In addition, a series resistor (R

S

) may be used in high-gain modes. 

Recommended component values are listed in