Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
136
Freescale Semiconductor
2.3.78
Port AD Interrupt Flag Register (PIF1AD)
2.3.79
Port R Interrupt Enable Register (PIER)
Read: Anytime.
Address 0x028D
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PIF1AD7
PIF1AD6
PIF1AD5
PIF1AD4
PIF1AD3
PIF1AD2
PIF1AD1
PIF1AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-75. Port F Interrupt Flag Register (PIF1AD)
Table 2-63. PIF1AD Register Field Descriptions
Field
Description
7-0
PIF1AD
Port AD interrupt flag—
Each flag is set by an active edge on the associated input pin. To clear this flag, write logic level 1 to the
corresponding bit in the PIF1AD register. Writing a 0 has no effect.
Each flag is set by an active edge on the associated input pin. To clear this flag, write logic level 1 to the
corresponding bit in the PIF1AD register. Writing a 0 has no effect.
1
1 Active falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
0 No active edge pending.
1
In order to enable the Key Wakeup function, need to set the ATDIENL first.
Address 0x028E
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
0
0
PIER4
PIER3
PIER2
PIER1
PIER0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-76. Port R Interrupt Enable Register (PIER)
Table 2-64. PIER Register Field Descriptions
Field
Description
4-0
PIER
Port R interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).