Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
138
Freescale Semiconductor
2.3.82
Port U Input Register (PTIU)
Table 2-66. PTU Register Field Descriptions
Field
Description
7,5,3,1
PTU
Port U general purpose input/output data—Data Register, Motor driver PWM output
Port U 7,5,3,1 pins are associated with the Motor PWM output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
Port U 7,5,3,1 pins are associated with the Motor PWM output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
• The SSD takes precedence over the Motor Driver and general purpose I/O function
• The Motor driver PWM takes precedence over the general purpose I/O function.
• The Motor driver PWM takes precedence over the general purpose I/O function.
6,4,2,0
PTU
Port U general purpose input/output data—Data Register, Motor driver PWM output, TIM0 channels 3-0
Port U 6,4,2,0 pins are associated with the Motor PWM output and TIM0 channels 3-0
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
Port U 6,4,2,0 pins are associated with the Motor PWM output and TIM0 channels 3-0
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
• The SSD takes precedence over the Motor Driver and and TIM0 and general purpose I/O function
• The Motor driver PWM takes precedence over the TIM0 and the general purpose I/O function.
• The TIM0 output function takes precedence over the general purpose I/O function if related channel is enabled
• The Motor driver PWM takes precedence over the TIM0 and the general purpose I/O function.
• The TIM0 output function takes precedence over the general purpose I/O function if related channel is enabled
1
1
In order TIM input capture to be function correctly, the corresponding DDRU bit shoud be set to 0. Also the corresponding SRRU
bit should be set to 0.
bit should be set to 0.
Address 0x0291
Access: User read
1
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-79. Port U Input Register (PTIU)
Table 2-67. PTIU Register Field Descriptions
Field
Description
7-0
PTIU
Port U input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.